** to designate keynote talk - 30 min Sponsored by:  
* to designate invite talk - 25 min
  to designate regular talk - 15 min

Sunday, March 14, 2021 Shanghai International Convention Center
Meeting Room:

Session I: Lithograpy/Etch joint session
Session Chairs: Leo Pang (D2S) / Ying Zhang (Naura)
13:30-13:35 Opening
   
**13:35-14:05 The latest development and results in advanced technoogy nodes patterning
  Rich Wise, Lam Research
**14:05-14:35 2-D Logic Device Scaling to Forksheet, and technical challenges to Nanosheet / Forksheet configurations
  David Xiao, IMEC
**14:35-15:05 Advanced Packaging Architectures for Advanced Heterogeneous Integration (HI)
  Ravi Mahajan, Intel
15:05-15:30 Coffee Break
   

Session II: Lithography Materials
Session Chair: Zhimin Zhu (Intel) / Xiaoming (Dow)
*15:30-15:55 Negative-tone imaging (NTI) for advanced lithography with EUV exposure to improve 'Chemical Stochastic'
  TORU FUJIMORI, FUJIFILM Corporation
15:55-16:10 Advanced Lithography Material Status toward 5nm Node and Beyond
  Koichi FUJIWARA, JSR Shanghai Co., Ltd.
*16:10-16:35 Progress and outlook towards High-NA EUV materials
  Jara Garcia Santaclara, ASML
16:35-16:50 High Performance Filtration for Bulk and POU filtration of EUV
  Lucia D’Urzo, Pall
16:50-17:05 Development of planarizing spin-on carbon material for high-temperature processes
  Runhui Huang, Brewer Science Inc.
   

Monday, March 15, 2021 Shanghai International Convention Center
Meeting Room:


Session III: Process and Simulation
Session Chair: Yuyang Sun (Mentor) /Da Yang (TEL)
*8:30-8:55 Contour based process characterization, control and hotspot prediction for semiconductor manufacturing
  AO CHEN, Mentor, a Siemens Business
8:55-9:10 Lithographic Simulator Based on Deep Learning with Graph Input
  Peng Xu, IMECAS
9:10-9:25 The Setting of Linewidth Reference on Photomask through Physical Process Modeling
  Rui Hu, Shanghai IC R&D Center
9:25-9:40 SEM Image Transformation between Litho Domain and Etch Domain
  Yan Yan,Shanghai IC R&D Center
*9:40-10:05 ML enhanced full-flow design guided wafer defect analysis and reduction
  Qian Xie, Mentor, a Siemens Business
10:05-10:20 Coffee Break
   

Session IV: Computational Lithography
Session Chair: Ken Wu (ICRD) /Yayi Wei (IME)
*10:20-10:45 Full Chip Curvilinear ILT with both Multi-Beam and VSB Mask Writers That Doubles Wafer Process Windows
  Leo Pang, D2S
*10:45-11:10 Optical Proximity Correction (OPC), Methodology and Limitations
  Yongqiang Hou, Shanghai IC R&D Center
11:10-11:25 Source and mask optimization with narrow-band semi-implicit scheme
  Yijang Shen, Guangdong University of Technology
*11:25-11:50 Simulation investigation of resolution enhancement techniques (RETs) for EUV single patterning of logic Via layers in 5nm node
  Boer Zhu, ASML
11:50-13:30 Lunch Break

Session V: Next Generation Lithography
Session Chair: Wei-Min Gao (ASML) / Imai-san (Mitokogyo)
**13:30-14:00 Update of >300W High Power LPP-EUV Source Challenge III for Semiconductor HVM
  Hakaru Mizoguchi, Gigaphoton
*14:00-14:25 193i lithography’s path to the future
  Stephen Renwick, Nikon Research Corp of America
*14:25-14:50 Nanoimprint Performance Improvements for High Volume Semiconductor Manufacturing

Keita Sakai, Canon Inc.
*14:50-15:15 Extending the capability of lithography with mechanical processesthan 20nm width materials
  Huigao Duan, Hunan University
*15:15-15:30 Coffee Break



Session VI: mask, inspection, overlay, and metrology equipment
Session Chair: Shiyuan Liu )HUST) / Chris Progler (Photronics)
*15:30-15:55 A New Generation Cost-efficient Laser Mask Writer for Mature Semiconductor Nodes

Peter Henriksson, Mycronic AB
*15:55-16:20 An innovative graphical platform for real time accurate AEI overlay prediction and rework control

Yaobin FENG, YMTC
*16:20-16:45 Feed-forward correction of on-product overlay using standalone alignment technology

Masahiko OKUMURA, Nikon Corporation
*16:45-17:10 Integrated optical metrology solutions for advanced IC fabrication

Jonee Li, Shanghai Precision Measurement Semiconductor Technology,Inc.
*17:10-17:35 Overlay metrology based on Mueller matrix scatterometry

Hao Jiang, Huazhong University of Science and Technology
*17:35-18:00 Reference Metrology Using 3D-PSD of Post-Etch LWR
  Masami Ikota, Hitachi High-Tech Corp.
Poster Session:
  Critical Dimension Uniformity Improvement of Negative Toned Developing Process for Hole Type Pattern
  Rui-Lin Zhang, Semiconductor Manufacturing International Corporation
  The photoresist developing ability study at different contact angle and mask transmission rate
  Chen Lijun, Shanghai Huali Microelectronics Corporation
  The Mechanism Study of Rounded AA Damage Defect after POLY Loop
  Zheng Haichang, Shanghai Huali Microelectronics Corporation
  Improving Scanner Alignment Accuracy by Wafer Alignment Optimization
  Ma Yuanzhao, Nikon Precision Shanghai
  Contour extraction for SEM image based on deep learning method
  Li Chen, Shanghai IC R&D Center
  Extreme edge uniformity control study in Poly-Si Planarization etch
  Minxiang Wang, Lam Research Service Co., Ltd
  Aberration analysis and control based on fully connected neural network
  Shuang Zhang, Shanghai IC R&D Center
  Mining Lithography Hotspots from Massive SEM Images Using Machine Learning Model
  Zhou Tao, Shanghai IC R&D Center
  MIX AND MATCH OVERLAY IMPROVEMENT STUDY ON NIKON IMMERSION SCANNER
  Ma Yuanzhao, Nikon Precision Shanghai