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China Semiconductor Technology International Conference (CSTIC) 2017
Plan now to participate at CSTIC 2017, one of the largest and the most comprehensive annual semiconductor technology conferences in China and Asia since 2000. Organized by SEMI,IMEC and IEEE-EDS , co-organized by IMECAS and ICMTIA(The Integrated circuit Materials Industry Technology Innovation Alliance), and co-sponsored by ECS, MRS and CEMIA(the China Electronics Materials Industry Association), CSTIC 2017 will be held March 12-13, 2017 in Shanghai, China, in conjunction with SEMICON China 2017. The conference will have nine symposiums cover all aspects of semiconductor technology with focus on manufacturing and advanced technology, including detail manufacturing processes, devices design, integration, materials, and equipment, as well as emerging semiconductor technologies, circuit design, and silicon material applications. Hot topics, such as memory technology, 3D integration, MEMS Technology will also be addressed in the conference.
**Full length manuscripts of accepted papers will be considered for publication in IEEE Xplore.
Date and Venue
March 12-13, 2017 Shanghai International Convention Center 上海国际会议中心 中国上海浦东滨江大道2727号 No.2727 Riverside Avenue Pudong, Shanghai 200120, China |
Distinguished Conference Keynote Speakers
Conference Chairman
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Partial list of other confirmed distinguished CSTIC 2017 invited speakers
Advanced Logic and Specialty Technologies for VLSI Manufacturing in fast expansion at China |
Min-hwa Chi, Sr, VP, SMIC |
Steep-slope device |
Dr. Qingtai Zhao, Forschungszentrum Julich |
Reliability enhancement of phase change memory using metal nitride liner |
Dr. SangBum Kim, IBM |
Comparative Experimental Study of the Improved MOSFET Matching by Using the Hexagonal Layout Style |
Prof. Salvador Pinillos Gimenez, Centro Universitario da FEI |
Monolithic 3D (M3D) Reconfigurable Logic Applications Using Extremely-Low-Power Electron Devices |
Prof. Woo Young Choi, Sogang University |
Analyzing the carrier mobility in two-dimensional MoS2 transistors |
Prof. Xinran Wang, Nanjing University |
Design Technology Co-optimization for Disruptive Patterning Schemes |
Prof.Puneet Gupta, UCLA |
The Path Forward: The Future of Optical Lithography |
Donis Flagello, CEO, Nikron Research America |
Molecular Force Modeling of Lithography |
Zhimin Zhu, Senior Scientist, Brewster Science |
The Insertion of extreme ultraviolet lithography (EUVL) from patterning perspective |
Weimin Gao, Senior cooperate application engineer, Synopsys |
Design Technology Co-optimization for Disruptive Patterning Schemes |
Prof. Puneet Gupta, UCLA |
Patterning Technology Inflections for the 10n and Beyond Logic Nodes |
Richard Wise, Managing Director, Lam Research, USA |
Advanced Plasma Etch technology and Applications |
Ganming Zhao, Senior Director, Applied Materials, China |
Atomic Precision Etching using a Low Electron Temperature Plasma |
Shahid Rauf, Senior Director, Applied Materials, Inc. |
Advanced technology for sub-10nm Patterning |
Naoki Inagaki, Project Leader and Director, Tokyo Electron Limited |
Interconnect Reliability Challenges for the 7nm Node and Below |
Tony Oates, IEEE Fellow; Senior Director, TSMC |
More-Moore Versus More-than-Moore and a Future of 50 Billion Connected Devices |
Aaron Voon-Yew Thean, Vice President of Logic Technologies, Professor in National Singapore University, IMEC |
Enabling Complex Patterning Through Materials Innovation |
Mark Saly, Manager, COE in Chemistry, AMAT |
Oxide based thin films for Current and Emerging Logic Applications |
Vijay Narayanan, Manager and distinguished research staff member, IBM |
Method of Forming a More Robust Sidewall Spacer with Lower k (Dielectric Constant) Value |
Tao Han, Member of Technical Staff, Globalfoundries Inc. US |
14 nm/10 nm Logic Node – Issues and Key Enabling Technologies |
Dr. Reza Arghavani, Managing Director of Technology, Lam Research Corporation |
Systems & Methodologies for Faster Process Development and Yield Ramps in the Nanoscale Era |
Charles Chu, Engagement Director, PDF Solution |
Review of thin film porosity characterization approaches |
Konstantin P. Mogilnikov, Principal Scientist, Leuven Instruments Co. Ltd (Jiangsu) |
Replacement Metal Gate (RMG) CMP for 14nm Transistor Scaling: Overview, Challenges and Opportunities |
Hong Jin Kim, Advanced Module Engineering (AME), Globalfoundries |
Abrasive Particle Trajectories and Material Removal Non-uniformity during Chemical Mechanical Polishing |
V. Rastegar, Clarkson University |
Chemical Mechanical Planarization – Building Stacked Devices |
Viorel Balan, Univ. Grenoble Alpes |
Challenges in CMP Defects of 7nm Device and its improvement opportunities |
Dr. Ji Chul Yang, Senior Member of Technical Staff (SMTS) and CMP Representative of Future Technology Roadmap Team, Globalfoundries |
Outsourced CMP for Rapid Development and Efficient Manufacturing |
Robert L. Rhoades, CTO, Entrepix, Inc. |
Nano Scale Interface Control for 28nm Cu CMP through Cu/Barrier Slurries |
Zhijie Zhang, Semiconductor Manufacturing North China (Beijing) Corp. |
Cu CMP Dishing and Erosion Optimization for Hybrid Bonding Technology |
GuangYi Wang, Wuhan Xinxin Semiconductor Manufacturing Co. Anji Microelectronics Co., Ltd. |
A New Acidic ILD Slurry Formulation for Advanced CMP |
Yi Guo, Dow Electronic Materials |
Time-dependent Clustering Model for Dielectric Breakdown with Variability |
Ernest Wu, STSM, IEEE Fellow, IBM T. J. Watson Research Center, USA |
New Approach For Full Chip Electrical Reliability Verification |
Frank Feng, Manager, Mentor Graphics, USA |
On the use of conductive atomic force microscopy to monitor resistive switching |
Mario Lanza, Young 1000 Talent Professor, Soochow University |
Physical Failure Analysis of Semiconductor Devices by Electron Probing and Transmission Electron Microscopy |
Dr. John Li, Principal Member Technical Staff, Globalfoundries, USA |
Key technologies and application demonstrations of 3D heterogeneous integration and FOWLP |
Prof. Kuan-Neng Chen, Prof, NCTU |
Process and Equipment Technology for Advanced Packaging |
Dr. Arvind Sundarraja/Scott Lin, Head, Asia Pacific Product Development Center, Applied Materials |
NEMI Shielding Technologies in RF Front End Modules |
Dr. Yifan Guo, VP Technology, ASE |
Fanout Technology and Development |
Dr. Scott Sikorski, VP Technology, SCL |
Role of Advanced Packaging in IC Scaling and Homogeneous and Heterogeneous Integration |
Dr. Hamid Azimi, VP, Intel |
3D & MEMS Vertical MEMS Probe Technology For Advanced Packaging |
Amy Leong, VP Marketing, Formfactor |
Neutral Beam Technology for Future Nano-devices |
Prof. Seiji Samukawa, IFS Tohoku University |
Extreme Miniaturization of Passive Electronic Devices by Self-Rolled-up Membrane Nanotechnology |
Prof. Xiuling Li, UIUC |
NOVEL ELECTRON DEVICES BASED ON LASER SCRIBED GRAPHENE |
Prof. Lu-Qi Tao, Tsinghua University |
Operation Fundamentals in Backend memories: programming window, retention and endurance |
Luca Perniola, CEA Tech |
Software Defined Chip: Technologies, Challenges and Opportunities |
Shaojun Wei,Tsinghua University |
Technology Advancement of Laminate Substrates for Mobile, IoT, and Automotive Applications |
Dr. Ken Lee, SimmTech |
CSTIC 2017 Agenda
Keynote & Invited Speakers
Keynote & Invited Speakers (2017)
Contact Us
Kelly Zhang, SEMI China
Tel: 86.21.6027.8556
Fax: 86.21.6027.8511
Email: [email protected]