** to designate keynote talk Sponsored by:
* to designate invite talk
  to designate regular talk

Joint Session: Lithograpy/Etch joint session (Symposium II & Symposium III)

Opening Remarks
Ying Zhang, Leo Pang
**The fast changing and advancing scaling technique and potential device infrastructure
David Xiao, Shanghai Integrated Circuit Research and Develop (ICRD) Center
**3D NAND Technology Cost Scaling Challenges and Solutions (9:30-10:00, June 22, Microsoft Teams Meeting)
Richard Yang, Fortune Precision Equipment, China
**Role of underlayers in novel patterning for EUV lithography
Doughlas Guerrero, Brewer Science, Inc.
**Considerations in seting up industry standards for photolithography process, historical perspectives, methologies, and outlook
Wu Qiang, Fudan University
 

Session II: Advanced Patterning

*Profile control technique for High Aspect Contact Etch utilizing Coverage Controllable ALD
Yoshihide Kihara, TEL, Japan
*5nm fin SAQP patterning challenges and perspective solutions
Qingjun Zhou, Naura, China
Pitch Walking Simulation and Process Window Evaluation of Self-Aligned Quadruple Patterning for Advanced Nodes
Xing Ke, Semiconductor Manufacturing International Corp., China
 

Session III: FEOL/MOL Etching

Modeling of advanced FinFET poly gate corner residue impacted by clogging
Xingyu Xiao, Semiconductor Manufacturing International Corp., China
Bitline Etch Process Development for 1y nm DRAM Manufacturing
Xing-Jun Yao, NAURA, China
*High aspect ratio etch challenges and proposed ICP etch solutions
Zhiqiang Liu, AMEC, China
*THE COMBINATION OF WF6 AND HBR FOR HIGH-ASPECT-RATIO CRYOGENIC DIELECTRIC ETCH
Vina Xu, AMEC, China
Approach for High transmission ratio power device pad etch with smooth sidewall and long MTBC
Dongming Zhou, AMEC, China
 
 

Session IV: Plasma Source and Wet Etch/Clean

*Mattson Novyka Selective Etch and Applications
Shanyu Wang, Mattson
SADP etch process development using PR core for sub 17nm DRAM
Li-Tian Xu, Naura, China
Beyond 20nm DRAM Capacitor Etch Challenge and Process Solution
Zengwen Hu, AMEC, China
Localized Pattern Loading Improvement of SOC Recess Process for Airgap Spacer Application
Bo Su, Semiconductor Manufacturing International Corp., China
 

Session V: BEOL Etching and Memory Etch

*Integrated etch solution for magnetic tunneling junction patterning
Yuxin Yang, Leuven Instruments, China
An Explanation of Wafer Center Arcing Defect
Jun Wang, SMIC, China
Hard mask etch process development for patterning 60nm magnetic tunnel junction
Xiaohui Li, Naura, China
200/150/100mm Compatible, ICP and CCP Etch Total Solutions
Yiming Zhang, Naura, China

Session VI: Other Etch and Patterning

*Trench Etch for SiC Power Devices
Qiushi Xie, Naura, China
Removing (sub)surface defects induced by Si wafer thinning processes enables high-performance backscattered electron detector
Zhu Chen, Shanghai University, China
Effectively improving local critical dimension uniformity of small hole arrays by photo resist treatment
Mimi Dai, AMEC, China
Advanced Ru Selective Etch for MEMS and Sub-3nm Applications
Chien-Pin Sherman Hsu, Avantor, Taiwan, China
 

Poster Session:

Tri layer mask dry etch process optimizing and wet effect for straight profile
Xiaobing Liu, Shanghai IC R&D Center
IMPROVING CIS WHITE PIXEL PERFORMANCE BY RAP PROCESS REPLACEMENT ON SYNDION FS TOOL IN VERTICAL TRANSFER GATE APPLICATION
Yiling Sun, Lam Research
Effects of Ion incident angles on Etching Morphology of Blazed Grating by IBE
Jie Yuan, Jiangsu Normal University
Balance of Spacer Profile Angle and Footing to Reduce Pitch Walking  in SADP Process
Chun-Kai Wang, Lam Research
GaN Etching with Inductively Coupled Plasma for Power Device Applications
Shizheng Li, Advanced Micro-Fabrication Equipment Company Inc.
Investigation of Fin Bowing Formation Mechanism During STI Etching by Virtual Fabrication
Li-Fei Sun, Lam Research
PROCESS WINDOW CHECK FOR FIN CUT FIRST SCHEME
Li-Fei Sun, Lam Research
Recipe Optimization to Reduce Arching and DA Shift Risk under Wafer Backside Dielectric Layers
Caigan Chen, Lam Research
Recipe Optimization to Reducearching and DA Shift under Wafer Backside Dielectric Layers
Bill Bian, Lam Research
Research on copper corrosion in copper interconnection cleaning process
Fuping Chen, ACM Research (Shanghai), Inc.
PSR Silicon Trench Profile Optimization in FinFET Fabrication
Zhengning Li, Semiconductor Manufacturing International Corporation (SMIC)
Investigation of Selective SiGe Etching Process for Advanced Semiconductor Technology
Peng Yang, Shanghai IC R&D Center
A Study on Impact of Gate Thickness on Device Performance for Advanced Node Logic Transistors
Xu Jia, Lam Research
The Effects of Etch Stop Layer Undercut on BEOL Electric Performance at Advance Node
Tianhao Zhang, Lam Research
Impact of Metal Line Roughness on RC Delay
Hexin Zhou, Lam Research
Research on Single RCA clean in high aspect ratio trench process
Fuping Chen, ACM Research (Shanghai), Inc.
Study on Inversed-taper Poly Profile as Solution of 3D Corner Residue
PengFei Lyu, Lam Research
Simulation Study on Different Integration Schemes to Form Single Diffusion Break
PengFei Lyu, Lam Research
Study on Process Improvement and Yield Enhancement of 40nm e-flash AIO Wet Strip
Zhiyuan Xu, Shanghai Huali Integrated Circuit Manufacturing Corporation
Enhanced WLC for ICP productivity
Wenbo Shi, Advanced Micro-Fabrication Equipment (AMEC)
Study and Optimazation of Photo Resistor Etch Back loop in HK Metal Gate
Yajie Li, Shanghai Huali Integrated Circuit Corporation
STUDY ON THE OPTIMIZATION OF FINFET ULTRA-SHALLOW JUNCTION ION IMPLANTATION PROCESS
Wenqiang Li, Shanghai Huali Integrated Circuit Corporation
THE INVESTIGATION OF DRY ETCH APPROACH TO REMOVE SILICON ANTIREFLECTIVE COATING AND SPIN-ON CARBON
Zhiqiang Xu, Shanghai Huali Integrated Circuit Corporation
N/P SPLIT BOUNDARY PROFILE IMPROVEMENT IN HIGH K METAL GATE DUMMY POLY REMOVE PROCESS
Huang Shan, Shanghai Huali Integrated Circuit Manufacture Corporation Shanghai
Improvement of Liner Wall Roughness on BARC Open and Related Theory Research
Linpeng Jiang, Shanghai Huali Microelectronics Corporation
Exploration and Optimization of Metal Gate Etch Back Process in Advanced Technology Node
Shaoxiong Liu, Shanghai Huali Microelectronics Corporation
Advanced Pulsing Control Tungsten Profile in DRAM Periphery Gate Etch
Zheng Ruan, Lam Research
Statistic big data analysis method used for Tilting mismatch problem solving
Rui Bao, Lam Research
Conductor Etch Advanced Function for sub-20nm DRAM Patterning
Yujia Zhong, Lam Research
15nm DRAM SADP patterning solution by capacitively coupled plasma etcher
Julia Zheng, Lam Research
Selective Wet-etching of GeSi in Multi-layer GeSi/Si Stacks
Jiajia Tian, Integrated Circuits Advanced Process R&D Center of IMECAS
Applied Sym3®M for High-Aspect-Ratio Al Line Etching
Liang Liao, Applied Materials (China), Inc.
Source drain recess profile effect on epi size modelling
Minxiang Wang, Lam Research
Via Contact Profile Effect on Metal-Via Resistance & Overlay Window
Jian Huang, Lam Research
Enhanced Passivation on Carbon Sidewall to Control Bowing During Hard Mask Open Etch Process
Arthur Jin, Lam Research
Profile Improvement in Aluminum Oxide Etch
Yingying Zhou, Lam Research
Hole Micro Twisting Improvement in a High Aspect Ratio Carbon Etch
Swen Jin, Lam Research
Hole Micro Uniformity Improvement in a High Aspect Ratio Carbon Etch
YaQian Jiang, Lam Research
Trench Kink Profile Improvement of Dual Damascene Etching Process
Kai Cui, ShangHai HuaLi Microelectronics Corporation
Hole shape modification in high aspect ratio carbon etch process
Junming Wang, Lam Research
LWR Improve of Oxide Mandrel Etch in SADP Scheme
Tianchen Kang, ShangHai HuaLi Microelectronics Corporation
Notching Reduction by Pulsed Low Frequency Bias Power during Deep Silicon Etch on SOI Substrate
Stan Zhang, Lam Research
Wafer Extreme Edge Feature Tilting Improvement
Shanshan Nie, Lam research
Temperature Controlled Dry Etch Trim Process for Silicon Film Planarization
Tao(McRee) Wang, Lam Research
Optimization of approach for metal contamination reduction
Meng-Yu Xie, NAURA
Optimization of Shallow Trench Isolation CD micro loading in advance CMOS
Guang Yang, NAURA
Research of ultra high aspect ratio silicon etching in 1y DRAM STI
Zheng Ji, NAURA
SNC SADP Spacer etch process development using carbon hard mask mandrel for sub advanced process DRAM
Hao Liu, NAURA
The Research of special gate morphology adjustment and its influence on electrical properties
Junjie Pan, HLMC
Method for Profile Control of Sigma-shaped Trench in SiGe Epitaxy Technology
Xuanting Zhu, HLMC
Silicon Partial Etch Defect Researches in BSI CMOS Image Sensor Process Product
Hebao Liu, SMIC