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Chinese
2020年6月27-29日
上海新国际博览中心

Symposium IV: Thin Film, Plating and Process Integration


(** to designate keynote talk, * to designate invite talk)

Sunday, March 15, 2020 Shanghai International Convention Center

Meeting Room: 3H+3I+3J

Session I:
Session Chair: Beichao Zhang
 
13:30-13:35 Chairman Remarks
  Beichao Zhang
**13:35-14:05 Enabling CMOS Logic Technology Scaling beyond FinFETs
  Bu Huiming, IBM Research
**14:05-14:35 Beyond Silicon: Low-dimensional Nanoelectronics
  Shu-Jen Han, HefeChip
14:35-15:00 Coffee Break
   


Session II:
Session Chair: Larry Zhao

**15:00-15:30 Exploring Aggressive BEOL Scaling Using Electrochemical ALD and ALE of Interconnect Materials
  Prof. Rohan Akolkar, Case Western Reserve University
**15:30-16:00 Process Innovations for Semiconductor Technology using Area Selective Atomic Layer Deposition
  Prof. Stacey Bent, Stanford University
*16:00-16:25 Evolution of FINFETS and The Role of Thin Films
  Rishikesh Krishnan, IBM
   


Monday, March 16, 2020 Shanghai International Convention Center
Meeting Room: 3H+3I+3J

Session III:
Session Chair: Huang Liu
 
*08:30-08:55 3D memory related technology update
  Hongbin Zhu, YMTC
*08:55-09:20 Design & Technology Co-Optimization in Advanced Node
  Dr. AbdelKarim Mercha, IMEC
*09:20-09:45 Arm Artisan SRAM IP Design in TSMC 22nm Process
  Dr. Bo Zheng, ARM
*09:45-10:10 Emerging Memories and their Opportunities
  Tseng Chiahsun, AMAT
10:10-10:30 Coffee Break
   


Session IV:
Session Chair: Jian Yan

*10:30-10:55 Fabrication and Performance Trade-offs of Future Interconnect Design and Material Options
  Dr. Jonathan Reid, Lam Research
*10:55-11:20 BEOL Interconnect Challenges and Solutions for Advanced Technology Node
  Zhu Huanfeng, Lam Research
11:20-11:35 Titanium Silicide Anneal Process Research for 14nm FinFET Technology
  Lan Jiang, HLMC
11:35-11:50 Enhancing high temperature adhesion performance via a renovated leadframe surface treatment
  Lois Liao Jinzhi, WinTech Nano-Technology Services Pte. Ltd.
11:50-12:05 Developments of Advanced Si Based Dry Removal and Clean
  Bo Zheng, NAURA
12:05-13:30 Lunch Break
   


Session V:
Session Chair: Xiaoping Shi

*13:30-13:55 PECVD and PEALD Low-k Silicon Carbonnitride Films for Microelectronic Applications
  Jim Leu, National Chiao Tung University
*13:55-14:20 Mechanically Stable Ultra-low k dielectric and Air-gap technology
  Mansun Chan, The Hong Kong University of Science and Technology
14:20-14:35 Some key modifications of theory required to understand the leakage current mechanisms for MIM capacitors used in DRAM technology
  Wai Shing Lau, Zhejiang University
14:35-14:50 Surface smoothing and roughening effects of high-k dielectric materials deposited by atomic layer deposition and their significance for MIM capacitors used in DRAM technology Part II
  Wai Shing Lau, Zhejiang University
14:50-15:20 Coffee Break
   


Session VI:
Session Chair: Li-qun Xia

*15:20-15:45 Film for Advanced Patterning and Profile Control
  Li Ming, Lam Research
*15:45-16:10 Dielectric Technologies for Advanced Logic and Memory Products
  Somnath Nag, AMAT
16:10-16:25 FDSOI SiGe morphology Optimization on boundary of AA and STI
  Jiaqi Hong, HLMC
16:25-16:40 Optimization of imperfect morphology for SiGe selective epitaxial growth
  Yongyue Chen, HLMC
16:40-16:55 Thin Film Processes: Abatement of Waste Gases from plasma assisted material processes
  Christopher P Jones, Edwards Ltd
   
Poster Session: Location: 5th Floor    
Coffee Break Study of Influence of STI Profile on HARP Gap-Filling Performance
  Kai Wang, Zhigang Zhang, Ping Wang, Lingzhi Xu, Shenzhou Lu, Andy Tan, Zhenjie Qiao, Kang Huang, Qimeng Wang, Duo Shan, Fan Bai, Fan Zhang, Chang Fu, Zhengyuan Zhao, Qin Sun, HLMC
  HARP Gap Fill Ability and Improvement of Defect Performance
  Xiang Li, Applied Materials

Multi Methods of Reducing Defects from DARC Process
  Xiang Li, Applied Materials (AMAT)

Applied Producer® Celera™ PECVD: Integrated Dual-Stress Liner Solution
  Tengfei Zhang, Applied Materials China
  The Producer GT HARP SACVD Chamber: Versatile Gap-Fill Technology

Wei Xia, Applied Materials China
  A Novel Methodology to Monitor Wafer Placement Shift in Laser Anneal

Yan Gui, HLMC
  Seam-Suppressed Tungsten Filling Technology for Challenging Structures

Zhen Chen, Applied materials
  A Study of DTI Gap Fill PEALD Oxide Process Tuning to Eliminate High-k/Substrate Peeling Defect in CMOS Image Sensors

Jiang Yu, Lam Research
  Investigation and characterization of silicon content in N-free anti-reflective layer Films

Luhang Shen, HLMC
  Cobalt Deposition Product Suite for 7nm and Beyond Contact
  MA NING, Applied Materials China

The investigation of domestic machines large-scale production in soak anneal process
  Yaoting Shen, HLMC

Metal Bump Defect Solution for Hot Al Metal Process
  Qingjun Ni, AMAT
  BEOL Cu Gap-fill Performance Improvement for 14nm Technology Node

Zhaoqin Zeng, Shanghai Huali Integrated Circuit Corporation
  Enhanced OLT for More Wafer Types in RTP Process

Luo Zhipeng, Applied Materials
  Gate Stack Solution Enabling DRAM Scaling Down to 1x nm Node

Guangyao Shen, Applied Materials China
  OPTIMIZATION OF DEPOSITION OF ALUMINUM NITRIDE BY PULSED DIRECT CURRENT REACTIVE MAGNETRON SPUTTERING
  Yiin-Kuen Fuh, National Central University

Study of Q-time Effect on Stress Nitride
  Songtao Lv, Applied Materials

Study of PREB Process in FDSOI
  Song Yang, Huali Microelectronics Corporation

Investigation of FDSOI Raised S/D Formation
  Ma Yanfei, Huali Microelectronics Corporation

IDT Structure Optimization Design Based on Lithium Niobate Substrate for SAW Filter
  LiKaixuan, Tianjin University of Technology

Studies of contact resistance and interface states with different metals on graphene in BEOL Interconnect Technology
  Weihao Lin, Shanghai IC R&D Center

Optimization of the CD uniformity (CDU) in silicon oxide spacer process for 5 nm Fin SAQP Process Flow
  Qingqing Wu, Shanghai IC R&D Center

Dielectric properties of Al2O3 films by pulsed DC magnetron sputtering
  Wen-Yu Cho, National Central University