Tom Thieme graduated from the University of Applied Sciences Berlin (Germany) in process and environmental engineering. Thereafter, 15 years as a professional in the global electronic and semiconductor industry gave him a distinguished experience in semiconductor related product support, marketing and sales.
Initially, as global product manager of TOTAL’s special chemical division, he approached the Asian silicon memory and CMOS semiconductor industry. This gave him a strong technical background on metal deposition processes for silicon and compound semiconductor application and wafer level packaging technologies. Since 2010 Tom is with LayTec and contributed very successfully to LayTec’s extraordinary success in the Greater China’s LED industry. As business development manager he helped our customers take full advantage of LayTec’s in-situ metrology products for compound semiconductor MOVPE processes. Based on his profound understanding of both, compound semiconductor customer needs and technology of integrated metrology he efficiently communicates the requests of our customers in the field back to LayTec’s R&D and application engineering teams. Since 2012 Tom is General Sales Manager of LayTec’s compound semiconductor division and since 2013 director marketing and sales. Abstract：
Reliability and yield limiting variances in power-electronic manufacturing-early detection by advanced in-situ monitoring
Semiconductor manufacturing is a battle for perfection, which not only includes the maximization of the device performance and device lifetime. The homogeneity of all key parameters across the whole wafer, on every wafer in every run within usually narrow target specifications is of importance, too. The ultimate target is 100% yield of the epi-process. Regardless of the material backbone of the specific device, this requires a high degree of homogeneity in terms of layer thickness, ternary or quaternary composition, doping level and interface and surface morphology. In this presentation we will show that in-situ metrology, especially the precise control of the wafer surface temperature and strain status of the layer, can be directly correlated with key performance parameters of power-electronic devices. |
