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Joint Session: Lithograpy/Etch joint session (Symposium II & Symposium III)
Session Chairs: Leo Pang (D2S) / Ying Zhang (Naura)
| Opening Remarks |
| Leo Pang, Ying Zhang |
| **The fast changing and advancing scaling technique and potential device infrastructure |
| David Xiao, Shanghai Integrated Circuit Research and Develop (ICRD) Center |
| **3D NAND Technology Cost Scaling Challenges and Solutions |
| Richard Yang, Fortune Precision Equipment, China |
| **Role of underlayers in novel patterning for EUV lithography |
| Doughlas Guerrero, Brewer Science, Inc. |
| **Considerations in seting up industry standards for photolithography process, historical perspectives, methologies, and outlook |
| Wu Qiang, Fudan University |
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Session II: Lithography Materials
Session Chairs: Zhimin Zhu (Intel) / Xiaoming Ma(Runbang)
| *Recent Aadvances in Extreme Ultravoliet Photoresists |
| Guoqiang Yang, Institute of Chemistry, Chinese Academy of Sciences / University of Chinese Academy of Sciences |
| The status of stochastic issues - Photon stochastic and Chemical Stochastic - |
| TORU FUJIMORI, FUJIFILM Corporation |
| *Advanced Lithography Material Status toward 5nm Node and beyond (9:30-10:00, June 16, Microsoft Teams Meeting) |
| Koichi FUJIWARA, JSR Shanghai |
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Session III: Process and Simulation
Session Chairs: Yuyang Sun (Mentor) /Da Yang (TEL)
| *Thickness Dependence of Properties of EUV Underlayer Thin Films |
| Jae Hwan Sim, DuPont Electronics and Industrial |
| *Process window, and process optimization in both Low and High NA EUV lithography for advanced logic technologies nodes |
| Yanli Li, Fudan University |
| A Study of Improved Design Rules through Allowing 45-degree Metal Lines |
| Xianhe Liu, Fudan University |
| *Critical pattern selection for full chip SMO application |
| Sikun Li, Shanghai Institute of Optics and Fine Mechanics |
Session IV: Computational Lithography
Session Chairs: Ken Wu (ICRD) /Yayi Wei (IME)
| *Machine Learning Post Lithography Resist 3D Structure Model For Full Chip Implementation |
| Xuelong Shi, Shanghai ICR&D Center |
| **Inverse lithography technology: 30 years from concept to practical, full-chip reality (9:00-9:30, June 16, Microsoft Teams Meeting) |
| Leo Pang, D2S, Inc. |
| *Gan-based fast mask near-field calculation |
| Yijiang Shen, Guangdong University of Technology |
| *Model-driven Deep Learning for Computational Lithography |
| Xu Ma, Beijing Institute of Technology |
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SESSION V: Next Generation Lithography
Session Chairs: Wei-Min Gao (ASML) / Imai-san (Mitokogyo)
| **Update of >300W High Power LPP-EUV Source Challenge IV for Semiconductor HVM |
| Hakaru Mizoguchi, Gigaphoton |
| *EPE and CD performance enhancement by “GT66A”, the next-generation immersion ArF lightsource |
| Takamitsu Komaki, Gigaphoton |
| **Nanoimprint Lithography Methods for Achieving sub-3nm Overlay |
| Keita Sakai, Cannon |
| *KrF Multi-Focal Imaging system for advanced and legacy applications |
| Will Conley, ASML |
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Session VI: mask, inspection, overlay, and metrology equipment
Session Chairs: Shiyuan Liu (HUST) / Chris Progler (Photronics)
| *Critical dimension metrology: from optical critical dimension (OCD) to X-ray critical dimension (XCD) |
| Xiuguo Chen, Huazhong University of Science and Technology |
| *A new generation cost-efficient laser mask writer, addressable up to the 90nm node |
| Youngjin Park, Mycronic Co., Ltd. |
| EUV vacuum system safety while maximizing process productivity |
| Zhen Ma, Edwards |
| DOSE CONTROL STRATEGY USING RANDOM LOGIC DEVICE PATTERNS AND MASSIVE METROLOGY IN A FOUNDRY HIGH VOLUME MANUFACTURING ENVIRONMENT |
| Kan Zhou, Shanghai Huali Microelectronics Corporation (HLMC) |
| *Patterning capability of surface plasmon imaging |
| Lihong Liu, Institute of Microelectronics, Chinese Academy of Sciences |
Poster Session:
| Utilizing Bossung Plot to calibrate OPC optical model |
| Jian Wang, Semiconductor Manufacturing International Corporation |
| CD-SEM contour extraction for complex features measurement |
| Ting He, Semiconductor Manufacturing International (Shanghai) Corporation |
| New model-rules-hybrid sbar placement strategy for 2D pattern |
| Ge Zhang, Semiconductor Manufacturing International Corporation |
| Simulation-based source and mask optimization for advanced nodes |
| Lianbo Luo, Semiconductor Manufacturing International Corporation, Shanghai |
| Process Window Integration Rule Check for BEOL in Advanced Tech Node |
| Xiaoyan Wang, Semiconductor Manufacturing International (Shanghai) Corporation |
| Kissing corner rounding improvement by special OPC |
| JIAO YUAN, Semiconductor Manufacturing International Corporation (SMIC) |
| Effect of high energy implantation on the photoresist for smaller size CMOS image sensor |
| Chen Hui, Shanghai Huali Microelectronics Corporation |
| OPC IMPROVEMENT OF CU VOID IN BEOL ADVANCED TECHNOLOGY NODE |
| Mudan Wang, Shanghai Huali Integrated Circuit Corporation |
| Stitching Process Development on 300mm Wafer CMOS BEOL for High Performance Chip Application |
| Xiaoxu Kang, Shanghai ICR&D Center |
| Alignment Mark Design and Evaluation for RDL and Cover layers using ASML Scanner |
| Yuhui Li, Shanghai Huali Integrated Circuit Corporation |
| Study on Feed-forward Overlay Control for Immersion Lithography |
| Guoping Liu, Shanghai Huali Integrated Circuit Corporation |
| Impact of Fin Cut Dimension and Density on Fin CD Uniformity |
| Min Jia, Semiconductor Manufacturing International Corporation (SMIC) |