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Tri layer mask dry etch process optimizing and wet effect for straight profile
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Xiaobing Liu, Shanghai IC R&D Center
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IMPROVING CIS WHITE PIXEL PERFORMANCE BY RAP PROCESS REPLACEMENT ON SYNDION FS TOOL IN VERTICAL TRANSFER GATE APPLICATION
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Yiling Sun, Lam Research
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Effects of Ion incident angles on Etching Morphology of Blazed Grating by IBE
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Jie Yuan, Jiangsu Normal University
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Balance of Spacer Profile Angle and Footing to Reduce Pitch Walking in SADP Process
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Chun-Kai Wang, Lam Research
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GaN Etching with Inductively Coupled Plasma for Power Device Applications
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Shizheng Li, Advanced Micro-Fabrication Equipment Company Inc.
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Investigation of Fin Bowing Formation Mechanism During STI Etching by Virtual Fabrication
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Li-Fei Sun, Lam Research
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PROCESS WINDOW CHECK FOR FIN CUT FIRST SCHEME
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Li-Fei Sun, Lam Research
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Recipe Optimization to Reduce Arching and DA Shift Risk under Wafer Backside Dielectric Layers
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Caigan Chen, Lam Research
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Recipe Optimization to Reducearching and DA Shift under Wafer Backside Dielectric Layers
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Bill Bian, Lam Research
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Research on copper corrosion in copper interconnection cleaning process
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Fuping Chen, ACM Research (Shanghai), Inc.
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PSR Silicon Trench Profile Optimization in FinFET Fabrication
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Zhengning Li, Semiconductor Manufacturing International Corporation (SMIC)
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Investigation of Selective SiGe Etching Process for Advanced Semiconductor Technology
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Peng Yang, Shanghai IC R&D Center
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A Study on Impact of Gate Thickness on Device Performance for Advanced Node Logic Transistors
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Xu Jia, Lam Research
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The Effects of Etch Stop Layer Undercut on BEOL Electric Performance at Advance Node
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Tianhao Zhang, Lam Research
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Impact of Metal Line Roughness on RC Delay
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Hexin Zhou, Lam Research
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Research on Single RCA clean in high aspect ratio trench process
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Fuping Chen, ACM Research (Shanghai), Inc.
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Study on Inversed-taper Poly Profile as Solution of 3D Corner Residue
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PengFei Lyu, Lam Research
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Simulation Study on Different Integration Schemes to Form Single Diffusion Break
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PengFei Lyu, Lam Research
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Study on Process Improvement and Yield Enhancement of 40nm e-flash AIO Wet Strip
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Zhiyuan Xu, Shanghai Huali Integrated Circuit Manufacturing Corporation
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Enhanced WLC for ICP productivity
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Wenbo Shi, Advanced Micro-Fabrication Equipment (AMEC)
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Study and Optimazation of Photo Resistor Etch Back loop in HK Metal Gate
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Yajie Li, Shanghai Huali Integrated Circuit Corporation
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STUDY ON THE OPTIMIZATION OF FINFET ULTRA-SHALLOW JUNCTION ION IMPLANTATION PROCESS
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Wenqiang Li, Shanghai Huali Integrated Circuit Corporation
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THE INVESTIGATION OF DRY ETCH APPROACH TO REMOVE SILICON ANTIREFLECTIVE COATING AND SPIN-ON CARBON
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Zhiqiang Xu, Shanghai Huali Integrated Circuit Corporation
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N/P SPLIT BOUNDARY PROFILE IMPROVEMENT IN HIGH K METAL GATE DUMMY POLY REMOVE PROCESS
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Huang Shan, Shanghai Huali Integrated Circuit Manufacture Corporation Shanghai
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Improvement of Liner Wall Roughness on BARC Open and Related Theory Research
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Linpeng Jiang, Shanghai Huali Microelectronics Corporation
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Exploration and Optimization of Metal Gate Etch Back Process in Advanced Technology Node
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Shaoxiong Liu, Shanghai Huali Microelectronics Corporation
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Advanced Pulsing Control Tungsten Profile in DRAM Periphery Gate Etch
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Zheng Ruan, Lam Research
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Statistic big data analysis method used for Tilting mismatch problem solving
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Rui Bao, Lam Research
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Conductor Etch Advanced Function for sub-20nm DRAM Patterning
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Yujia Zhong, Lam Research
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15nm DRAM SADP patterning solution by capacitively coupled plasma etcher
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Julia Zheng, Lam Research
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Selective Wet-etching of GeSi in Multi-layer GeSi/Si Stacks
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Jiajia Tian, Integrated Circuits Advanced Process R&D Center of IMECAS
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Applied Sym3®M for High-Aspect-Ratio Al Line Etching
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Liang Liao, Applied Materials (China), Inc.
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Source drain recess profile effect on epi size modelling
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Minxiang Wang, Lam Research
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Via Contact Profile Effect on Metal-Via Resistance & Overlay Window
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Jian Huang, Lam Research
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Enhanced Passivation on Carbon Sidewall to Control Bowing During Hard Mask Open Etch Process
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Arthur Jin, Lam Research
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Profile Improvement in Aluminum Oxide Etch
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Yingying Zhou, Lam Research
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Hole Micro Twisting Improvement in a High Aspect Ratio Carbon Etch
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Swen Jin, Lam Research
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Hole Micro Uniformity Improvement in a High Aspect Ratio Carbon Etch
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YaQian Jiang, Lam Research
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Trench Kink Profile Improvement of Dual Damascene Etching Process
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Kai Cui, ShangHai HuaLi Microelectronics Corporation
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Hole shape modification in high aspect ratio carbon etch process
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Junming Wang, Lam Research
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LWR Improve of Oxide Mandrel Etch in SADP Scheme
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Tianchen Kang, ShangHai HuaLi Microelectronics Corporation
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Notching Reduction by Pulsed Low Frequency Bias Power during Deep Silicon Etch on SOI Substrate
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Stan Zhang, Lam Research
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Wafer Extreme Edge Feature Tilting Improvement
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Shanshan Nie, Lam research
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Temperature Controlled Dry Etch Trim Process for Silicon Film Planarization
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Tao(McRee) Wang, Lam Research
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Optimization of approach for metal contamination reduction
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Meng-Yu Xie, NAURA
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Optimization of Shallow Trench Isolation CD micro loading in advance CMOS
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Guang Yang, NAURA
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Research of ultra high aspect ratio silicon etching in 1y DRAM STI
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Zheng Ji, NAURA
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SNC SADP Spacer etch process development using carbon hard mask mandrel for sub advanced process DRAM
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Hao Liu, NAURA
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The Research of special gate morphology adjustment and its influence on electrical properties
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Junjie Pan, HLMC
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Method for Profile Control of Sigma-shaped Trench in SiGe Epitaxy Technology
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Xuanting Zhu, HLMC
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Silicon Partial Etch Defect Researches in BSI CMOS Image Sensor Process Product
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Hebao Liu, SMIC
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