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Fisher Zhang 张震宇 General Manager, Director & Auto Compute Business Unit Manager, Teradyne 泰瑞达全球汽车与计算事业部总监 |
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摘要 / Abstract AI is no longer an emerging concept—it is already deployed at scale across cloud infrastructure, software defined vehicles (SDV)/ADAS, and edge intelligence. As these applications push chips toward unprecedented integration, heterogeneous packaging, and higher power density, the resulting challenges extend beyond design and manufacturing into the test floor. This talk highlights how test becomes the gating factor for time to market when devices demand both higher coverage and more realistic mission mode validation. We focus on three test stressors. First, coverage and DFT at scale: larger SoCs and chiplet systems drive exploding pattern volume and tighter tradeoffs between coverage, throughput, and cost. Second, thermal realism: advanced devices operate under dynamic power and thermal gradients that can mask failures or create overkill unless thermal conditions are actively controlled and repeatable. Third, quality closure: automotive and AI infrastructure require rigorous traceability, regression confidence, and faster program releases despite constrained test engineering capacity. We map these needs to an integrated solution stack combining digital ATE, system level test (SLT) with active thermal control, and workflow automation. Teradyne’s approach includes collaboration with EDA partners for design to test efficiency and a software ecosystem that supports DevOps style practices (automation, regression, and continuous improvement) to accelerate releases while strengthening quality. |
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