Marc Greenberg is the Director of Product Marketing for DDR Controller IP at Synopsys. Marc has 13 years of experience working with DDR Design IP and has held DDR Technical and Product Marketing positions at Denali and Cadence prior to joining Synopsys. Marc has a further 10 years experience at Motorola in IP creation, IP management, and SoC Methodology. Marc holds a five-year Masters degree in Electronics from the University of Edinburgh in Scotland.
Topic & Abstract:
Architectural Options for LPDDR4 Implementation in Your Next Chip Design
LPDDR4 is the first JEDEC specification that specifies two DDR DRAM channels per die, and packages with four LPDDR4 DDR DRAM channels, giving chip architects new options when designing chips that connect to LPDDR4. This presentation will review the ways to take advantage of this native multichannel LPDDR4 capability. It will discuss how you can to divide memory traffic across the channels of LPDDR4, how to activate the low-power features of LPDDR4, how to make the electrical connection to LPDDR4, how to floorplan the chip design, and key features of the LPDDR4 memory subsystem. |
