| ** | to designate keynote talk - 30 min | Sponsored by: |
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| * | to designate invite talk - 25 min | |||
| to designate regular talk - 15 min |
Sunday, March 14, 2021 Shanghai International Convention Center
Meeting Room:
Session I: Design for Resilience and Robustness
Session Chairs:
| **13:30-14:00 | Electronic Design Automation for Emerging Technologies |
| Giovanni De Micheli,EPFL Lausanne | |
| *14:00-14:25 | TBD |
| Frank Feng | |
| *14:25-14:50 | Multi-GPU Acceleration for Global Placement |
| Yibo Lin, Peking University | |
| 14:50-15:05 | Stochastic Circuit Design Based on Exact Synthesis |
| Zhufei Chu, Ningbo University | |
| 15:05-15:25 | Coffee Break |
Session II: Design for Deep Learning
Session Chair:
| *15:25-15:50 | Proactive Supply Noise Mitigation and Design Methodology for Robust VLSI Power Distribution |
| Masanori Hashimoto, Osaka University | |
| *15:50-16:15 | Advancements on Parasitic Extraction Research and Related Challenges |
| Wenjian Yu, Tsinghua University | |
| *16:15-16:40 | TBD |
| Wei-Kai Shih | |
| 16:15-16:40 | Investigating the Impact of Supply Noise for Nano-Meter VLSI: Is the Supply Noise Margin Threshold Always Hard? |
| Cheng Zhuo,Zhejiang University | |
| 16:40-16:55 | Modeling of CMOS transistors from 0.18μm process by Artificial Neural Network |
| Jiahao Wei, Fudan University |
Monday, March 15, 2021 Shanghai International Convention Center
Meeting Room:
Session III: Design for Resilience and Robustness
Session Chair:
| **8:30-8:40 | Announcement of ACM SIGDA Eastern China Chapter |
| Cheng Zhuo，Zhejiang University, China | |
| **8:40-9:10 | Ensuring System-Level Resilience for Embedded Systems |
| Prof. Ulf Schlichtmann, Technical University of Munich | |
| *9:10-9:35 | Valid Test Pattern Identification for VLSI Adaptive Test |
| Tianming Ni, Anhui Polytechnic University | |
| 9:35-9:50 | Effective Radiation Damage to Floating Gate of Flash Memory |
| Chun-Zhang Chen, University of Chinese Academy of Sciences(UCAS) | |
| 9:50-10:05 | A Smart Resistor-based Highly Digital Temperature Sensor with Improved Supply Sensitivity in CMOS Technology |
| Yuhang Shui, Zhejiang University | |
| 10:05-10:20 | Noise Enhancement Effect in Auditory Neural Encoding for Spiking Neural Networks |
| Chen Wang, Zhejiang University | |
| 10:20-10:40 | Coffee Break |
Session IV: Design for Deep Learning
Session Chair:
| *10:40-11:05 | Hardware/Software Co-Design of Deep Learning Accelerators |
| Yiyu Shi, Duke University | |
| *11:05-11:30 | In-Memory Computing towards the POS/w era ---an algorithm–architecture co-design approach |
| Li Jiang , Shanghai Jiaotong University | |
| 11:30-11:45 | A LOW-BIT QUANTIZED AND HLS-BASED NEURAL NETWORK FPGA ACCELERATOR FOR OBJECT DETECTION |
| Jiaming Huang, Shanghai Jiao Tong University | |
| 11:45-12:00 | A Multi-Core RISC-V Processor for CNN Accelerator |
| Zhang Li, Zhejiang University | |
| 12:00-13:30 | Lunch Break |
Session V: EDA for AI
Session Chair:
| *13:00-13:55 | TBD |
| Meng Li, Facebook Inc. | |
| 13:55-14:10 | MAPPING CONVOLUTIONAL NEURAL NETWORKS ONTO NEUROMORPHIC CHIP FOR SPIKE-BASED COMPUTATION |
| Chenglong Zou, Peking University | |
| 14:10-14:25 | Nonlinear quantization for in-memory multi-bit MAC in SRAM array |
| Xunzhao Yin, Zhejiang University | |
| 14:25-14:40 | ApproxDNNFlow: An Evaluation and Exploration Framework for DNNs with Approximate Multipliers |
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Jide Zhang, Fudan University |
| 14:40-15:00 | Coffee Break |
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Session VI: Designing Future Computers
Session Chair:
| *15:00-15:25 | A Co-Design Framework of Neural Networks and Quantum Circuits Towards Quantum Advantage |
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Weiwen Jiang, University of Notre Dame |
| 15:25-15:40 | A Novel Toffoli Gate Design Using Quantum-dot Cellular Automata |
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Zhufei Chu,Ningbo University |
| 15:40-15:55 | The Study of TSV Induced and Strained Silicon Enhanced Stress in 3D-IC |
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Jindong Zhou, ShanghaiTech University |
| 15:55-16:10 | Design of Ternary Logic Based on ReRAM Crossbars |
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Weiyi Liu, Yanan Sun, Weifeng He, Weikang Qian, Zhongwei Jiang, Shanghai Jiao Tong University |
| Poster Session: | |
| A 241-uW Full Functional Speach Recognizer with Leveled VAD and Low Power Scheme | |
| LIANG Jun, Hangzhou Natinalchip S&T Co.,Ltd. | |
| An Economic Layout Solution with 20 um Scribe Line and Integrated Test Pad Based on 55 nm Platform | |
| Senior Engineer, Shanghai Huali Microelectronics Corporation | |
| A MobileNet Accelerator with High Processing-Element Efficiency on FPGA | |
| Tao Su, Sun Yat-sen University | |
| An Evaluation Framework for Computing-in-Memory Architecture | |
| Yuanqing Cheng, Beihang University | |
| Isolated word speech recognition based on BNN and its hardware implementation | |
| Di Gao, Zhejiang University | |
| Distributed Efficient Performance Modeling for Analog CircuitEthernet | |
| Liu Xin, Peking University | |
| Automated recognition of wafer backside image based on a hierarchical model | |
| Junjun Zhuang, Lam Research | |
| A Fast Bump Current Estimation Method using Chip Power Model | |
| Yufei Chen, Zhejiang University | |
| Deep-Learning-based software for epileptic focus detection | |
| Qinming Zhang, Zhejiang University | |
| A Homeostasis Based Expeditious Training Method in Spiking Neural Networks for Pattern Recognition | |
| Guanbin Yang, Peking University | |
| Improving Sidewall Roughness Performance through Shorten Phase Time RAP Process on Syndion tool in Deep Silicon Etching | |
| Sun Yiling, Lam Research | |
| Energy Efficiency Optimization with Early-Stage Workload Hotspots for Switched-Capacitor Converters in Embedded System | |
| Linfeng Zheng, ShanghaiTech University | |
| Automatic Digital Modeling for Analog Blocks in Mixed-Signal Verification | |
| Yangyang Leng, Tsinghua University | |