** to designate keynote talk - 30 min Sponsored by:  
* to designate invite talk - 25 min
  to designate regular talk - 15 min

Sunday, March 14, 2021 Shanghai International Convention Center
Meeting Room:3C+3D

Session I:Lithograpy/Etch joint session (II & III)
Session Chair:Kafai Lai / Ying Zhang
13:30-13:35 Opening Remarks
**13:35-14:05 The latest development and results in advanced technoogy nodes patterning
  Rich Wise, Lam Research, US
**13:05-14:35 2-D Logic Device Scaling to Forksheet, and technical challenges to Nanosheet / Forksheet configurations
  David Xiao, IMEC
*14:35-15:05 TED
   
15:05-15:20 Coffee Break
   

Session II:Advanced Patterning
Session Chair: Ying Zhang (Naura)
*15:20-15:50 Patterning challenges and perspetive solutions for advanced technology nodes
  Da Yang, TEL, US
*15:50-16:20 Advanced Materials and process technology for Patterning
  Aiay Bhatnagar, AMAT, US
16:20-16:35 DEEP AND VERTICAL POLYIMIDE ETCHING
  Yuwei Kong, NAURA Technology Group Co., Ltd., Beijing
   


Monday, March 15, 2021 Shanghai International Convention Center
Meeting Room:3C+3D
 
Session III:FEOL/MOL Etching
Session Chair: Tom Ni (AMEC)
9:00-9:15 Tunable Step Coverage Of In-Situ PE-ALD In Etch Chamber For Sidewall Protection During 3D NAND High Aspect-Ratio Etch
  Jingdong Yan, Lam research
*9:15-9:45 Innovative Future Etch Technology by Atomic-order control
 

Yoshihide Kihara, Tokyo Electron Limited

*9:45-10:15 Fin Self-Aligned Quadruple Patterning (SAQP) Process Development with Domestic Made Tools
  Yushu Yang, ICRD, China
10:15-10:30 Coffee Break
   

Session IV:Plasma Source and Wet Etch/Clean
Session Chair:Tom Ni (AMEC)
*10:30-11:00 Practical Solutions to the Challenges of Quantitative Radical Species Sensoring in Process Plasmas
  Jianping Zhao, Tokyo Electron America
*11:00-11:30 Advanced dry removal technology for patterning
  Hua Chuang, Mattson, US
11:30-11:45 Release Process Development for MEMS Micro-Bridge Structure
  Bo Zhang, HHGRACE
11:45-13:00 Lunch Break
   

Session V: BEOL Etching and Memory Etch
Session Chair:Jianping Zhao (TEL)
*13:00-13:30 The latest development and results on CCP etch applications
  Xingcai Su, AMEC, China
*13:30-14:00 Perspective on Plasma Etching in Advanced Packaging
  Yuanwei Lin, NAURA Technology Group Co., Ltd., Beijing
14:00-14:15 Simulation-Assisted Ion Angle Tuning in High Aspect-ratio (HAR) Etch for Wafer Edge Bottom Etch Enhancement

Jingdong Yan, Lam research
14:15-14:30 A study of inter-via CD and PEB amount correlation in dual damascene process
  Xinruo Su, Semiconductor manufacturing North China Corporation
14:30-15:00 Coffee Break



Session VI: ALE and Patterning
Session Chair:Yahui Huang (Naura)
*15:00-15:30 New Frontiers of Device Fabrication with Atomic Precision

Peter Ventzek, TEL, US
*15:30-16:00 The Novel Etching Process for Dense Array Magnetic Tunneling Junctions ManufacturingCurrent in VHF Plasma Sources

Taiyen Peng, Leuven Instruments
16:00-16:15 Cleaning PWA s in Electronics


Patrick Duchi, Inventec Chemicals Performance

16:15-16:30 Manufacturing Process Optimization of Polycrystaline Aluminum and Aluminum Alloy on SiO2/Si


Ping Linda Zhang, Richmond Star Hi-Tech Consulting Inc. ;
16:30-16:45 The Etching Morphology of Silver Study by Inductively Coupled Ar-Based Plasmas


Qingqing Lian, Zhongwei Jiang, NAURA

       
Poster Session:    

THE IMPROVEMENT OF AL-CU ALLOY CL-CORROSION RESISTANCE
  zoushifeng, HHGrace
  Study on Low Power Back-side Deep Trench Isolation Etching on Stack-BSI CMOS Image Sensor
  Zhuo Yin, Peking University
  Optimization of a Photoresist Trim Process with ICP Reactor
  Tianyin Sun, Lam Research
  Selective TiN vs W Etch for 3nm and Below Applications
  Chien-Pin Sherman Hsu, Avantor
  Novel Wet Etch Technology of Film Uniformity Tuning Through EOS AUT System
  Bowen Dai, Lam Research
  FinFET Gate Etch modeling by Coventor SEMulator3D?
  Hexin Zhou, Lam Research
  Application of Metastable Activated Radical in Advanced Strip Process
  ZHANG XIAO, Lam Research
  Pre-Silicidation Clean Product for 5nm and Beyond Contact
  Biran Zhang, Applied Materials (China)
  Gate Cut Patterning Scheme Simulation and Defect Modelling by SEMulator3D?
  Sun Li Fei, Wang Qing Peng, Zhang Ji Hong, Chi Yu Shan, Lam Research
  HNA Wet Etching Optimization in Wafer Thinning of BSI Process
  PengFei Lyu, Lam Research
  Improving Sidewall Roughness Performance through Shorten Phase Time RAP Process on Syndion tool in Deep Silicon Etching
  Sun Yiling, Lam Research
  MRAM MTJ Ion Beam Etching Simulation
  Caigan Chen, Lam Research
  FinFET Work Function Metal Recess Loading Study by AMMP and Low Duty Cycle of Bias Pulsing
  Caigan Chen, Lam Research
  AMAT SALD W for high AR via gap fill application
  Qingjun Ni, Applied Materials
  Si3N4 plasma etching study for optimized morphology performance
  Quanbao Li; Xiaohui Ren; Jihong Zhang; Yushan Chi, Lam Research
  Line Etch with HBr Cure Uniformity Study in Plasma Etch
  Xiaohui Ren, Lam Research
  Silicon Wafer Cleaning Optimization With Ozonated DI Water
  Jia Xu, Lam Research
  Silicon Wafer Uniformity and Roughness Control by Spin Etch D and Spin Etch E on Wafer Thinning
  Pin Chang, Li, Lam Research
  Study on characteristics of ion beam emitted from optical system of ion source
  Yongjie Hu, Jiangsu Normal University
  Etch Front Flatness Modification at Wafer Extreme Edge in a High Aspect Ratio Process
  Junming Wang, Lam Research
  Aegis Sidewall Protection in Fin STI Etching
  Tao Wang, Lam Research
  Structural and Electrical Properties of Ti-C Thin Films for Metal Gate
  Kamale Tuokedaerhan, Xinjiang University
  High Aspect Ratio Silicon Etch with High Selectivity to Tungsten
  Chun Gao, Lam Research
  Peeling Defect Studying with N2/H2 Plasma during Carbon-based Recess Etch
  Tao, Ye, Lam Research
  Bias Pulsing Plasma Etching for Polysilicon Gate Profile Control
  Yan He, Beijing NAURA Microelectronics Equipment CO.