Dr. CP Hung is currently the Vice President of Corporate R&D, ASE Group (Advanced Semiconductor Engineering) , responsible for next generation products development with integrated technologies and enabling chip, package and system holistic design solution. His previous roles in ASE were VP of Corporate Design, VP of Central Engineering / Business Development and VP of Logistic Service Integration.
He has 41 patents on packaging structure, process, substrate and characterization technology, also has published over 30 conference/ journal papers.
CP Hung receives his Ph.D. from Department of Electrical and Electronic Engineering, University of Paisley, U.K Topic & Abstract：
New Era 3D-Interconnection in SiP Technology
As System on Chip (SoC) technology towards to the limit of Moore’s Law, System in Package (SiP) has being implemented to provide alternative / complete toolbox for new generation products. Together, SoC with SiP will continue to enrich various system integrating solutions.
One of the key technology of SiP is the 3D IC interconnection, which has demonstrated in the semiconductor industry with steady manufacturability. This presentation will share the outlook for the upcoming new era of Through Silicon Via (TSV) in microelectronics toward the bright future of both IoT’s Terminal and Cloud applications. |
