Cassandra Melvin
Global Product Manager, SC/FEC, Atotech


Cassandra Melvin received her BS in Business Management and Neuropsychology at Rensselaer Polytechnic Institute and is Global Product Manager for Semiconductor and Functional Electronics Coatings at Atotech Deutschland GmbH. She is responsible for a product portfolio that includes electrolytic and electroless plating processes used in chip manufacturing and packaging, as well as lead frame and connector production.

Prior to joining the Atotech team, she held the position of Business Manager at the SUNY Polytechnic Institute (formerly the College of Nanoscale Science and Engineering) focusing on technical programs for semiconductor chemistry and equipment. She also held various project and program management roles in (semiconductor) operations and IT at SUNY.

Cassandra's written work has been published in leading technical magazines and presented at key conferences globally. She is a member of the SEMI Power Electronics Committees for Europe and is Chairwoman of the SEMI Women in Technology group.


As electro-mobility gains momentum, there is increasing pressure on the power semiconductor supply chain to enhance existing technologies. To satisfy the requirements for next generation power semiconductors in HEV/EV and e-mobility products, power packages must provide higher reliability and power density, better energy efficiency and management, and reduced package size.

A new electroplating system addresses these requirements. The new system enables a more efficient and cost effective method for embedding power chips with simultaneous metal deposition on both wafer sides. Additional system features provide technical benefits for embedded technologies and enable further miniaturization of power semiconductor packages to comply with future product requirements. Power management is a primary concern – particularly for thick Cu heat sink requirements – and the new tool delivers the benefit of thick Cu deposition up to 50µm for optimized dissipation.

Additional tool benefits include: 1) handling and processing of Taiko wafers with ≥50µm thickness, 2) significant warpage compensation using dual side metallization 3) individual control of plating parameters for each wafer side for plating on different design layouts and Cu thicknesses, 4) plating of up to 50µm Cu on wafer scale, and 5) improved manufacturing efficiency with 25 percent fewer process steps, thereby leading to 6) a cost per wafer reduction of 25 percent.

This paper will discuss how the new system's features enable these benefits and will present key process results as demonstrated in the EmPower consortium.