** to designate keynote talk Sponsored by:
* to designate invite talk
  to designate regular talk

Session I: Emerging Computing Technology

**Solving Optimization Problems with Nanoelectronic Neuromorphic Circuits
Dmitri Strukov, University of California, Santa Barbara
*Novel thermal properties for smart computing (9:00-9:30, June 15, Microsoft Teams Meeting)
Suhas Kumar, Sandia National Lab
*Nonvolatile-memory Based Compute-in-memory Technology for Energy Efficient DNN Accelerator
Wonbo Shim, Seoul National University of Science and Technology
*System-technology Co-optimization for 3D Monolithic Memory-centric Computing
Bin Gao, Tsinghua University
Zinc-alloyed HfO2 synaptic RRAM with operating voltage and switching energy enhancement
Jun Lan, Southern University of Science and Technology

Session II: Novel Ferroelectric Devices

*Optimization of endurance and operation voltage in ferroelectric field effect transistor memory devices
Kechao Tang, Peking University
NOVEL NEGATIVE-FEEDBACK METHOD FOR WRITING VARIATION SUPPRESSION IN FEFET-BASED COMPUTING-IN-MEMORY MACRO
Weikai Xu, Peking University
A study on the Hf0.5Zr0.5O2 Ferroelectric Capacitors Fabricated with Hf and Zr Chlorides
Jun-Fei Zheng, Entegris Inc
A NOVEL ANTI-FERROELECTRIC NEGATIVE CAPACITANCE TUNNELING FET WITH MITIGATED SUBTHRESHOLD SWING DEGRADATION ISSUE
Shaodi Xu, Peking University

Session III: New Two-dimensional and Oxide Semiconductor Devices

**Going where silicon cannot reach: Print-in-place and recyclable electronics from nanomaterials
Aaron Franklin, Duke University
*Enabling 3D Monolithic Integration using Oxide-Semiconductor-based Transistors (10:00-10:30, June 15, Microsoft Teams Meeting)
Xiao Gong, National University of Singapore
*The Road to Compatible with and Beyond Silicon Circuits for 2D Materials (9:30-10:00, June 15, Microsoft Teams Meeting)
Peng Zhou, Fudan University
Air Stable High Mobility ALD ZnO TFT with HfO2 Passivation Layer Suitable for CMOS-BEOL Integration
Wenhui Wang, Southern University of Science and Technology
 

Session IV: Advanced Devices and Characterization

*Low Frequency Noise of Advanced Memory and Logic Devices
Eddy Simoen, IMEC
*Study about self-heating effects in gate-all-around nanowire transistors
Sangwan Kim, Sogang University
Effects of gate metal and channel shape on the variability of junctionless field-effect transistors
Xinhe Wang, Tsinghua University
CFET 6T HD SRAM DESIGNS WITH 3NM DESIGN RULE
Xiaona Zhu, Fudan University
 

SESSION V: Advanced Process Technology

*Process Window Optimization of DRAM by Virtual Fabrication
Joseph Ervin, Lam Research
*IC Technologies and Systems for Green Future
Min-hwa Chi, SiEn Integrated Circuits
Device Uniformity Improvement and Power Off Leakage Reduction by Tuning the Thickness and Profile of NMOS Work Function Metal in 28HKMG Process
Zhejun Liu, Shanghai Huali Integrated Circuit Corporation
Influence of Ion Implantation on Silicon Pits Defect Formation in Oxide Etch Process
Zhiqiang Xiao, Semiconductor Manufacturing North China (Beijing) Corp.
Future of wafer-to-wafer bonding to overcome Non-Volatile Memory density limitations
BELINDA DUBE, Systemplus Consulting
PATHFINDING BY PROCESS WINDOW CHECK: ADVANCED DRAM CAPACITOR PATTERNING PROCESS WINDOW EVALUATION USING VIRTUAL FABRICATION
Qingpeng Wang, Lam Research
 

Poster Session:

Systematic Study of Temperature and VDD Impact to Read Current and Standby Leakage of SRAM in FinFET Technology
Yijun Zhang, SMIC
Satellite Defects Caused by Insufficient Rinse of HR Photo Development with High Transmittance Mask
WenSheng Xu, Shanghai Huali Microelectronics Corporation
T2000 ISS FT Solution Using CP Light Source
Gong Bin, Advantest
A WAFER-ON-WAFER NON-UNIFORM HIGH POWER THERMAL MODEL FOR 3D CHIP PACKAGE
Song Wang, Xi'an UniIC Semiconductors
AMAT High Energy Implanters Offer High Throughput and Uniformity
Shasha Wang, Applied Materials China
Impact of Topology of Trench Gate Bottom Corner for Power MOSFET and IGBT
Min-hwa Chi, SiEN
Investigation of removing standing wave effect during 14nm litho process
Xueqiang Liu, HLMC
A Novel Method using Barc EB Process to improve split gate flash erase capability
Yaohui Zhou, Central Semiconductor Manufacturing Corporation (CSMC)
Optimization of Metal Line Thickness & CD and Effect on RC Delay
PengFei Lyu, Lam Research
Linear doping Boron in SiGe layer for PMOS device improvement
Wangxin Nie, Shanghai Huali Integrated Circuit Corporation
A proper method to extract the effective resistance of the MOSFET source/drain metal interconnection
ShiShuai Ma, Semiconductor Manufacturing International Corporation
Picosecond Imaging Circuit Analysis of CMOS Circuits Using High NA SIL Measurement
Shang Chih Lin, GALLANT PRECISION MACHINING CO., LTD.
Study of HDPCVD temperature profile’s impact on IMD EM issue in 90nm CIS BEOL
Jie Yang, Lam Research
Novel SOI Based Pseudo-inverter: Experimental and Simulation Research
Sherzod Khaydarov, Fudan university
FABRICATION OF RAISED SIGE SOURCE AND DRAIN BASED ON SIGE CHANNEL FOR ADVANCED FDSOI TECHNOLOGY
Yongyue Chen, Shanghai Huali Integrated Circuit Corporation
A PIN photodetector based on a RF-SOI substrate
Jingjing Chou, Fudan University
55nm Ultra-Low Power Platform 3.3V I/O Device Reliability Improvement
Zhao Guo, Shanghai Huali Microelectronics Corporation
MBIST Repair Mechanism and Implementation
Haijing Wu, Advantest
EVALUATION OF DIFFERENT CUT APPROACHES ON ADVANCED BEOL SELF-ALIGNED DOUBLE PATTERNING SCHEME
Chia Lin Lu, Lam Research
The Research of Decreasing SIGE Loss in Fully Depleted Silicon on Insulator (FDSOI) Devices
Che Siyuan, Shanghai Huali Microelectronics Corporation
Delamination Investigation of Epoxy Molding Compound on SOP Device
Hongjie Liu, HHCK
Improvement of CMOS device performance by a combination of spike and flash annealing
KeCheng Chen, Shanghai Huali Integrated Circuit Corporation
Evaluation of Picosecond Ultrasonic Technology for in-die measurements of metal depth in Metal Line Array in 3D NAND Process
Yanwei Liu, YANGTZE MEMORY TECHNOLOGIES CO.,LTD
Negative Capacitance Double-Gate Vertical Tunnel FET With Improved Subthreshold Characteristics
Guoliang Tian, Institute of microelectronics, Chinese Academy of Sciences
Sub-20nm DRAM Metal Gate Depth Loading Improved by Advanced Pulsing Plasma Application
Kevin Yao, Lam Research
Research on Vt Window Improvement Process of 55nm SONOS eFlash Cell
Shipu Li, Shanghai Huali Microelectronics Corporation
Suppression of TSV Leakage of UTS CIS by Optimizing SE/TE Profile and Uniformity
Zherui Cao, Shanghai Huali Integrated Circuit Corporation
The effective method of enhancing WIW uniformity in Poly CMP
Mengxia Li, Applied Material
ALD Characteristic Study of Al2O3 Film Deposited by a Dual Single-Wafer Process Chamber
Ge Zhang, Piotech Inc.
A novel SiGe heterojunction phototransistor applicable in wide spectral range
Yin Sha, Beijing University of Technology
The study of dislocation stress memory for NMOS boost
Dandan Jin, Shanghai Huali Integrated Circuit Corporation
High Quality Flatness of AP2LT Platen for HE XP penetration Implant
Ruijun Cui, Applied Materials
Full Well Capacitance of Small Size CMOS Image Senor: Improvement and stability control
Xiaoyu Li, Shanghai Huali Microelectronics Corporation
Device non-uniformity improvement for yield enhancement
Qian Liu, Applied Materials
Defect Reduction with advanced lithographic filter
Robb Fang, Cobetter Filtration Equipment Co.,Ltd
Low-k Anneal Process Development in Logic Devices
Kang Yang, Applied Materials (China)
Research on Process and Reliability Performance of SONOS Memory Base on Ultra-Low Power Technology
Qiang Liu, Shanghai Huali Microelectronics Corporation
FCVD ANNEAL PROCESS FOR FIN CD LOSS REDUCTION STUDY
Jun Yin, HLMC
Precision DARC Film Tuning to Meet DRAM D1y Customer Requirement
Levy Wang, Applied Materials (China), Inc.China
The influence of the film adjustment for deep trench isolation (DTI) filling on the thermal quality in CMOS Image Sensor
Yaguo Cai, Shanghai Huali Integrated Circuit Corporation
FDC High Order Analysis
Yiwen He, Shanghai Huali Integrated Circuit Corporation
Addressable WAT test of domestic Semitronix tester
Yangyang Xing, Shanghai Huali Integrated Circuit Corporation
40nm backside optimization and improvement
Lu Xu, Shanghai Huali Integrated Circuit Corporation
IMD Block Etch Defect Improve in AIO Etch Process
Ningpu Hou, ShangHai HuaLi Microelectronics Corporation-Advanced Module Technology Development Division
37nm Defect Reduction Study for ILD0 CMP of 14nm FinFET Process
Yunhong Hou, Applied Materials
A Study of LDMOS with High Breakdown Voltage and Low On-Resistance in 22nm Technology
Zhenchao Sui, Semiconductor Manufacturing North China (Beijing) Corporation
A study of the effect of SiGe on the inverse narrow width effect in 28nm Process
Yang Li, Shanghai Huali Integrated Circuit Corporation
Improving the Device Performance of LDMOS through the Optimization of Structure
Shuang Jiao, Shanghai Huali Microelectronics Corporation
Bottom dielectric isolation to suppress sub-fin parasitic channel of vertically-stacked horizontal gate-all-around Si nanosheets devices
Lei Cao, Institute of Microelectronics of Chinese Academy of Sciences and University of Chinese Academy of Sciences
Influence of Parasitic Capacitance and Resistance on Performance of 6T-SRAM for Advanced CMOS Circuits Design
Yanna Luo, Institute of Microelectronics of the Chinese Academy of Sciences
Methods of Reducing Etching Residue Defects in Back End of Line for Semiconductor in 28nm Technology
Shanshan Chen, Shanghai Huali Integrated Circuit Corporation
Innovations in Soldering Materials and Optimization of Solder Paste Printing and Inspection Parameters for System-in-Package Assembly
Evan Griffith, Indium Corporation
EVO head for CMP planarization improvement in advanced wafer house
Chienchung Li, AMAT
Applied ALD SiN solutions to improve device mobility in advance DRAM
Ze Yuan, AMAT
Hard Mask Open Tilting Improvement with Advanced Source Coil
Xiantao Luo, AMAT
W Deposition Uniformity improvement with process tuning
Bruce Fan, Lam Research
Optimization and Demonstration of Low-Voltage NMOS for RF Switch Application in 65nm SOI Technology
Zhaozhao Xu, Huahong Semiconductor (Wuxi) Limited
The Optimization of breakdown voltage and specific on-resistance of 30V n-VDMOS with short channel
Xiaoqing Cai, HuaHong Grace Semiconductor Manufacturing Corporation
Study of Breakdown Voltage improvement of High-voltage NLDMOS in width direction
Wenting Duan, HuaHong Grace Semiconductor Manufacturing Corporation
Improve the On-Resistance for 80V nLDMOS with STI technology in 0.18 um BCD process
Xiaoming Zhang, HuaHong Grace Semiconductor Manufacturing Corporation
Low crosstalk and high Q-factor inductor based on multiple guard-ring design
Xiaodon Wang, SMIC
Flicker noise characterization of LDMOS in FinFET technology
Yuning Guo, SMIC
LOW ON-RESISTANCE LDMOS WITH STEPPED FIELD PLATES FROM 12V TO 40V IN 300-MM 90-NM BCD TECHNOLOGY
Zhaozhao Xu, Huahong Semiconductor (Wuxi) Limited
High endurance SONOS technology improved by design and process optimization
Pingsheng Zhou, HHGrace