Symposium Chair: Prof. Weikang Qian, University of Michigan-Shanghai Jiao Tong University Joint Institute, China

** to designate keynote talk - 30 min Sponsored by:  
* to designate invite talk - 25 min
  to designate regular talk - 15 min

Sunday, March 17, 2024Shanghai International Convention Center
Meeting Room: 3E

Session I: Keynote Session I
Session Chair: Weikang Qian, Shanghai Jiao Tong University
13:30-13:35 Opening Remarks
  Weikang Qian, Shanghai Jiao Tong University
**13:35-14:05 Scale-out Chiplet-based Systems: Architecture, Design and Pathfinding
  Puneet Gupta, University of California, Los Angeles(UCLA)
**14:05-14:35 Photonic-Electronic Design Automation
  Jiang Xu, Hongkong University of Science and Technology
14:35-14:50 Coffee Break

Session II: Design Technology Co-Optimization
Session Chair: Yu-Guang Chen, National Central University
*14:50-15:15 Diffusive/Quantum Carrier Transport and Multiphysics Simulation Methods of Advanced Electronic/Optoelectronic Devices
  Wenchao Chen, Zhejiang University
*15:15-15:40 Design Technology Co-Optimization Methods for Advanced Logic Nodes
  Xingsheng Wang, Huazhong University of Science and Technology
*15:40-16:05 Machine Learning for Device Modeling (MLDM) in the DTCO Eco-system
  Lining Zhang, Peking University
*16:05-16:30 Exploring AI-in-the-Loop For Physical Design Verification DFM/DTCO EDA
  Yongfu Li, Shanghai Jiao Tong University

Monday, March 18, 2024 Shanghai International Convention Center
Meeting Room: 3E

Session III: Keynote Session II
Session Chair: Xunzhao Yin, Zhejiang University
**8:30-9:00 Ultra-broadband RF Front-end SoC using 0.18um CMOS technology
  Jianguo Ma, Zhejiang Lab

Session IV: Hardware Security
Session Chair: Xunzhao Yin, Zhejiang University
*9:30-9:55 Logic Locking over TFHE for Securing User Data and Algorithms
  Masanori Hashimoto, Kyoto University
9:55-10:10 A Customized Model for Defensing Against Adversarial Attacks
  Jiang Sun, ShanghaiTech University
10:10-10:25 Coffee Break

Session V: EDA
Session Chair: Pingqiang Zhou, ShanghaiTech University
*10:25-10:50 Logic Synthesis based on Semi-tensor Product of Matrices
  Zhufei Chu, Ningbo University
10:50-11:05 Logic Synthesis for XOR-AND Graphs via Reed-Muller Representations
  Zhufei Chu, Ningbo University
11:05-11:20 Integration of Shift Left Updates into Logic Synthesis and Macro Placement
  Xinfei Guo, Shanghai Jiao Tong University
11:20-11:35 TimingDTH: Timing-driven placement with Deep Three-Head reinforcement learning
  Shuai Yuan, Shanghai Jiao Tong University
11:35-11:50 Decoupling Capacitor Optimization for 2.5D-ICs with Deep Reinforcement Learning Technique
  Haiyang Feng, Zhejiang University
11:50-13:30 Lunch Break

Session VI: AI Accelertors
Session Chair: An Zou, Shanghai Jiao Tong University
*13:30-13:55 Optimizing Architecture and Algorithm for Privacy-Preserving Machine Learning
  Jongeun Lee, Ulsan National Institute of Science and Technology
*13:55-14:20 Efficient and Robust Hardware for Neural Networks
  Li Zhang, Technical University of Darmstadt
*14:20-14:45 Algorithm and Hardware Codesign for Brain-inspired Neuromorphic Computing
  Aili Wang, Zhejiang University
14:45-15:00 A Hardware Accelerator for Sparse Computing Based on NVDLA
  Yizhou Chen, Zhejiang University
15:00-15:15 Integer Arithmetic-Based and Activation-Aware GELU Optimization for Vision Transformer
  Zihan Zou, Southeast University
15:15-15:30 Coffee Break
Session VII: Advanced Circuit and System Design
Session Chair: Aili Wang, Zhejiang University
*15:30-15:55 A Journey of High-Density Associative Memories based on Ferroelectric Content Addressable Memories
  Xunzhao Yin, Zhejiang University
*15:55-16:20 Navigating Aging Effects: Concepts and Implementation in Reliable Computing Systems
  Yu-Guang Chen, National Central University
16:20-16:35 Enhance the Real-Time Performance of FPGA through Partial Dynamic Reconfiguration
  An Zou, Shanghai Jiao Tong University
16:35-16:50 A 16-bit 8MSPS SAR ADC with Configurable Low-Power Comparator
  Yidan Liang, Zhejiang University
Poster Session:
  Data Flow Graph Partitioning Method for CGRA Temporal Mapping Based on Bayesian Optimization
  Yihan Hu, Fudan University
  Verification of 400GbE with Optical Modules on an FPGA Platform
  C.-Z. CHEN, Peng Cheng Laboratory
  A transient enhanced output capacitor-less LDO with adaptive biasing and spike reduction
  Qianxi Cheng, Peking University
  Design of large-scale power battery safety monitoring system
  Zixiang Yan, Hangzhou Dianzi University
  Chaorun Li, Peking University
  Runtime Configurable Approximate Computing System for Simulated Annealing Algorithm
  Shi Jian, Shanghai Jiao Tong University
  An 18.3~42.1GHz octave frequency tuning class-C quadcore VCO achieving 204.5 dBc/Hz FOMT
  Shan Lu, Institute of microelectronics of the Chinese Academy of Sciences
  Effective Resistance Estimation for Large Circuits Using Random Walk Algorithm
  Jinyu Zhang, Empyrean Technology Co., Ltd.
  A Novel Smart Sampling Approach with Broader Compatibility in Semiconductor Manufacturing
  Tianyue Lai, Fujian Jinhua Integrated Circuit Co. Ltd.
  Designing and Accelerating Spiking Neural Network based on High-level Synthesis
  Heng Zi, Beijing University of Posts and Telecommunications
  Zhinan Chen, Fudan University
  A 106TOPS/W SRAM Compute-In-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI
  Yiqi Meng, Zhejiang University
  Application of Community Detection based Parallel MOEA/D Algorithm in RF Power Amplifier Circuit Design
  Jiejin Zhou, Fudan University
  A Hardware Accelerator of the Convolutional Spike Neural Network Based on STDP Online Learning
  Qinxin Chen, Zhejiang University