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Chinese
2020年6月27-29日
上海新国际博览中心

Symposium II: Lithography and Patterning


(** to designate keynote talk, * to designate invite talk)

Sunday, March 15, 2020 Shanghai International Convention Center
Meeting Room:5th Floor Yangtze River Hall
 
Joint Session: Symposium II and Symposium III-Lithography/Etch
Session Chairs: Kafai Lai / Ying Zhang
13:30-13:35 Opening Remarks
  Kafai Lai / Ying Zhang
**13:35-14:05 TBD
  Shingo Yoshikawa, DNP
**14:05-14:35 Advanced Memory Patterning Challenges and Perspective Solutions
  Jeongdong Choe, DRAM
**14:35-15:05 The Law that Guides the Development of Photolithography Technology and the Methodology in the Design of Photolithographic Process
  Qiang Wu, ICRD
15:05-15:20 Coffee Break
   
Session II: Computational Lithography
Session Chairs: Yayi Wei / Weimin Gao
*15:20-15:40 High-NA EUV lithography enabling cost-effective shrink patterning
  Jara G. Santaclara, ASML
*15:40-16:00 Accurate etch modeling with high-volume metrology and deep-learning technology
  Wei Yuan, ICRD
16:00-16:15 AI Computational Lithography
  Xuelong Shi, ICRD
16:15-16:30 Accurate mask model approaches for wafer hot spot prediction and verification
  Young Mog Ham, Photronics
16:30-16:45 Etch Proximity Correction Based on Machine Learning
  Rui Chen, IMECAS
16:45-17:00 Simulation Study for Typical Design Rule Patterns and Stochastic printing failures in 5 nm Logic Process with EUV Photolithographic Process
  Yanli Li, ICRD
   
Meeting Room:5F
Parallel Session: Novel technologies
Session Chairs: Leo Pang/ Wang Yueh
*15:20-15:40 TBD
  Thomas Schrubel, Zeiss
*15:40-16:00 EUV lithography and metrology for more Moore
  Yasin Eckinci, Paul Scherer Institute
16:00-16:15 Mitigation of microbridging defects in EUV lithography through advanced filtration technologies
  Toru Umeda, Nihon Pall Ltd.
16:15-16:30 Second order diffraction EUV interference lithography for the study of highresolution EUV resists
  Xiaolong Wang, Paul Scherer Institute
16:30-16:45 Development of 90 nm & 5 nm patterning materials for lithographic technology
  Hai Deng, Fudan University
   
Monday, March 16, 2020 Shanghai International Convention Center
Meeting Room: 5th Floor Yangtze River Hall
 
Joint Session: Symposium II and Symposium IX-DTCO
Session Chairs: Cheng Zhuo/ George Lu
08:30-08:35 Opening Remarks
  Cheng Zhuo/ George Lu
**08:35-09:05 Monolithic 3D enabled Processing-in-SRAM Memory
  Vijaykrishnan Narayanan, Pennsylvania State University
**09:05-09:35 TBD
  Steffen Schulz, Mentor Graphics
**09:35-10:05 Full Chip Curvilinear ILT in a Day
  Leo Pang, D2S
10:05-10:20 Coffee Break
   
Session IV: Multiple patterning
Session Chairs: Ban-Ching Ho / Zhimin Zhu
*10:20-10:40 Multi-focal imaging; Principles and application for improving DOF in an Advanced 3D NAND Via Layer
  Will Conley, Cymer
*10:40-11:00 Considerations of missing hole defect in EUV patterning
  Hidetami Yaegashi, TEL
*11:00-11:20 A Study of Image Contrast, Stochastic Defectivity, and Optical Proximity Effect in EUV Photolithographic Process under Typical 5 nm Logic Design Rules
  Qiang Wu, ICRD
*11:20-11:40 DuPont's Embedded Layer Technology that Enables Advanced Lithography
  Mingqi Li, Dupont Electronics
11:40-11:55 The topography effect on the lithography patterning control for VLSI fabrication
  Dongyu Xu, Huali
11:55-12:10 Advanced Patterning technology by evolution on process integration and equipment
  Inagaki Naoki, TEL
12:10-13:40 Lunch Break
   
Session V: Tool, Mask & Metrology
Session Chairs: Motokatsu Imai / Qiang Wu
**13:40-14:10 Challenge of High Power LPP-EUV Source with Long Collector Mirror Lifetime for Semiconductor HVM
  Hakaru Mizaguchi, Gigaphoton
*14:10-14:30 Multi-beam mask writer MBM-1000
  Hiroshi Matsumoto, NuFlare
*14:30-14:50 Line Width and Roughness Measurement of Advanced FinFET Features by Reference Metrology
  Mamsami Ikota, Hitachi High Tech
*14:50-15:10 Nanoimprint Performance Improvements for High Volume Semiconductor Manufacturing
  Keita Sakai, Canon Inc.
15:10-15:25 High Speed Wafer Geoemtry on Silicon Wafers Using Wave Front Phase Imaging for Inline Metrology
  Jan Gaudestad, Wooptix
15:25-15:40 Productivity Improvement with Rapid Detection in Coater and Developer System
  Hiromitsu Maejima, TEL
15:40-15:55 Coffee Break
   
Session VI: Process & Material
Session Chairs: Xiaoming Ma / Hai Deng
*15:55-16:15 Advanced Lithography Material Status toward 5nm Node and beyond
  Kouichi Fujiwara, JSR
16:15-16:30 How to improve' Chemical Stochastic' in EUV lithography ?
  Toru Fujimori, Fujifilm Corp.
*16:30-16:50 Novel Spin on Planarization Technology by Photo Curing SOC
  Hikaru Tokunaga, Nissan Chemicals
*16:50-17:10 VASE innovation for ultrathin film characterization
  Zhimin Zhu, Brewer Science
17:10-17:25 Evolution of Underlayer Materials for Enhancement of Lithographic Patterning
  Jae Hwan Sim, DuPont Electronics & Imaging Korea Technology Center
*17:25-17:45 Are Surfaces of Silicon Hardmasks Adaptive?
  Xianggui Ye, Brewer Science


Poster Session: Location: 5th Floor
Coffee Break Impacts of RTP pyrometer offsets on wafer overlay residue

Lv Jian, HLMC  
  Mix and Match Overlay Improvement of 55nm M1 Layer On Nikon Immersion Scanner
  Ma Yuanzhao, Nikon Precision Shanghai
  Study of Positive Tone Photoresist Thin Film Homogeneity at Nanoscale During Lithographic Process Using Massive Cluster Secondary Ion Mass Spectrometry
  Mingqi Li, Dupont Electronics & Imaging
  APPLICATIONS OF SPARSE AND COMPACT RESIST MODELING IN ADVANCED NODE IMPLANT LAYER
  MudanWang, HLMC
  Optical Scatterometry Modeling of 5 nm Structures with RCWA Method and Perfectly Matching Layer (PML) Boundary Conditions
  Aihua Yang, Shanghai IC R&D Center
  EVALUATING THE PROCESS PERFORMANCES OF BINARY, PSM AND OMOG MASKS IN 14NM TECHNOLOGY NODE
  Xie Weimei, Chen Yanpeng, Yu Shirui, HLMC
  Study of alignment & overlay strategy in 14nm lithography process
  Lulu Lai, HLMC
  Litho Process Optimization to Improve Overlay Measurement in Thick PR Layer
  Jiantao Wang, HLMC
  Effects of Electron Beam on Photo Resist Shrinkage and Critical Dimension in SEM Measurement
  Yuyang Bian, HLMC
  Enlarge Process Window of BSI in DTI Loop :A Novel OPC Approach to Add SRAF
  Qiao Yanhui, HLMC
  Solvement of TEOS residues during 19NAND process
  Fang Ma, Shanghai Huali Microelectronics Corporation
  Critical Dimension Uniformity Improvement of Negative Toned Developing Process for Hole Type Pattern
  Rui-Lin Zhang, Semiconductor Manufacturing International Corp
  Mask fidelity improvement using different MPC techniques
  Mohamed Ramadan, Photronics