Dr. David Haynes
Vice President of Specialty Technologies and Strategic Marketing, CSBG, Lam Research Corp.

讲师简介 / Speaker Bio

David gained a B.Eng and PhD in Materials Engineering from Swansea University. His PhD thesis was in the field of organic semiconductors for electronic and optoelectronic applications.
In his professional career, David has accrued more than 25 years of experience in the Semiconductor Capital Equipment and research instrumentation sectors. Focused on new technology development, he has a strong process background in plasma etch and deposition for optoelectronics, photonics, MEMS, Power and RF Electronics, as well as advanced chip packaging technologies.
Building on this technical knowledge, David has a proven track record in developing strategic business partnerships, specializing in new technology developments and introduction of enabling process capabilities to leading semiconductor fabs worldwide.
David Joined Lam Research in June 2016. He is currently Vice President of Strategic Marketing in Lam’s Customer Support Business Group and is responsible for Lam’s strategy in Specialty Technologies.

摘要 / Abstract

A wide range of applications in automotive electronics, smart energy, industrial applications and 5G cellular communications are increasingly dependent on advanced power semiconductors and power management ICs (PMICs).
Deep reactive ion etching (DRIE), initially developed for the fabrication of MEMS devices1, has also become one of the key enabling technologies used in the fabrication of Si based power devices.
This is particularly true of the high aspect ratio trench etch requirements associated with fabrication of super junction (SJ) MOSFETS and the formation of deep trench isolation (DTI) features in advanced bipolar, CMOS, DMOS based PMIC devices. However, at the same time, fabrication of other power devices such as insulated gate bipolar transistors (IGBTs) and shielded gate MOSFETs rely on the etching of high precision shallow trenches, typically using steady state etch processes. The ability to address all these requirements in a single process tool without compromising on etch quality allows for power device makers to have operational flexibility to address a broad product mix.
In the paper we will provide an update on how we have been working to address these challenges with our recently introduced Syndion® GP product. We will show how development of our deep silicon etch hardware and process capabilities is resulting in significant improvements in on-wafer results and supporting next generation power device fabrication. Such challenges include the continuous improvement of process productivity, improved profile control, achieving smoother etched sidewalls, and improving uniformity of both etch depth and feature CD.