Date: 13:30-15:00, Monday, March 15, 2021
Venue: Shanghai International Convention Center
Room: 5F
Dr. Jianyin Peng
Executive President, Nuclei

Jianyin Peng, PhD, graduated from ZheJiang University. At present she is the executive president of Nuclei, responsible for the overall management, especially for R&D and sales and marketing. She has been engaged in the field of CPU processor design for more than 15years. Built Synopsys ARC R&D Center in China from scratch while she was the Senior R&D Manager in Synopsys. Also served as the R&D manager of Marvel ARM CPU Department.


· RISC-V发展情况
· RISC-V指令集架构介绍
 √ 标准指令集
 √ P扩展指令集
 √ V扩展指令集
 √ 安全等其他指令集
· RISC-V处理器技术发展趋势

Title: The Great Opportunity for RISC-V in AIoT Era
RISC-V is a free and open ISA (instruction-set architecture) enabling a new era of processor innovation through open standard collaboration. The RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
RISC-V ISA was started in May 2010 from the Parallel Computing Laboratory(Par Lab) at UC Berkeley, of which Prof. David Patterson was Director. The RISC-V Foundation ( is a global nonprofit association based in Switzerland. Founded in 2015 as the RISC-V Foundation with 29 members, RISC-V is now a truly global organization with over 750 members in more than 50 countries.
RSIC-V is designed with many advantages: simple, clean-slate design, modular, designed for extensibility/specialization, stable. It’s perfectly for various AIoT applications. This report will cover:
· The latest status update of RISC-V
· The history of RISC-V
· RISC-V ISA Details
 √ Baseline ISA
 √ P-extension ISA
 √ V-extension ISA
 √ Security ISA & others
· The trend of RISC-V processors