** to designate keynote talk - 30 min Sponsored by:  
* to designate invite talk - 25 min
  to designate regular talk - 15 min

Symposium Chair: Beichao Zhang
Symposium Co-chairs: Zhen Guo, Xiaoping Shi, Chao Zhao, Huang Liu, Jiang Yan and Chih-Chao Yang

Online Conference  
Parallel Symposium Oral Sessions: June 29-July 17, 2020

Session I:
** Enabling CMOS Logic Technology Scaling beyond FinFETs

Dechao Guo, IBM Research
Session II:
** Exploring Aggressive BEOL Scaling Using Electrochemical ALD and ALE of Interconnect Materials

Prof. Rohan Akolkar, Case Western Reserve University
* Evolution of FINFETS and The Role of Thin Films

Rishikesh Krishnan, IBM
Session III:
* 3D memory related technology update

Hongbin Zhu, YMTC
* Design & Technology Co-Optimization in Advanced Node

Dr. AbdelKarim Mercha, IMEC
Session IV:
* Fabrication and Performance Trade-offs of Future Interconnect Design and Material Options

Jonathan Reid, Lam Research
* BEOL Interconnect Challenges and Solutions for Advanced Technology Node

Zhu Huanfeng, Lam Research

Enhancing high temperature adhesion performance via a renovated leadframe surface treatment

Din-Ghee Neoh, Atotech

Development of advanced Si Based Dry Removal and Clean

Chun Wang, NAURA
Session V:
* Dielectric Technologies for Advanced Logic and Memory Products

Terrance Lee, Applied Materials

Some key modifications of theory required to understand the leakage current mechanisms for MIM capacitors used in DRAM technology

Wai Shing Lau, Zhejiang University

Surface smoothing and roughening effects of high-k dielectric materials deposited by atomic layer deposition and their significance for MIM capacitors used in DRAM technology Part II

Wai Shing Lau, Zhejiang University
Session VI:
* Mechanically Stable Ultra-low k dielectric and Air-gap technology

Mansun Chan, The Hong Kong University of Science and Technology
  ICE Treatment Uniformity Optimization Study in Tungsten CVD Metal Gate Fill
  Ao Yang, Lam Research

Thin Film Processes: Abatement of Waste Gases from plasma assisted material processes

Christopher P Jones, Edwards Ltd

Conference Poster Session: June 26-July 17, 2020

  Study of Influence of STI Profile on HARP Gap-Filling Performance
  Kai Wang, Zhigang Zhang, Ping Wang, Lingzhi Xu, Shenzhou Lu, Andy Tan, Zhenjie Qiao, Kang Huang, Qimeng Wang, Duo Shan, Fan Bai, Fan Zhang, Chang Fu, Zhengyuan Zhao, Qin Sun, HLMC
  HARP Gap Fill Ability and Improvement of Defect Performance
  Xiang Li, Applied Materials

Multi Methods of Reducing Defects from DARC Process
  Xiang Li, Applied Materials

Applied Producer® Celera™ PECVD: Integrated Dual-Stress Liner Solution
  Tengfei Zhang, Applied Materials China
  The Producer GT HARP SACVD Chamber: Versatile Gap-Fill Technology

Wei Xia, Applied Materials China
  A Novel Methodology to Monitor Wafer Placement Shift in Laser Anneal

Yan Gui, HLMC
  Seam-Suppressed Tungsten Filling Technology for Challenging Structures

Zhen Chen, Applied materials
  A Study of DTI Gap Fill PEALD Oxide Process Tuning to Eliminate High-k/Substrate Peeling Defect in CMOS Image Sensors

Jiang Yu, Lam Research
  Investigation and characterization of silicon content in N-free anti-reflective layer Films

Luhang Shen, HLMC
  Cobalt Deposition Product Suite for 7nm and Beyond Contact
  MA NING, Applied Materials China

The investigation of domestic machines large-scale production in soak anneal process
  Yaoting Shen, HLMC

Metal Bump Defect Solution for Hot Al Metal Process
  Qingjun Ni, Applied Materials
  BEOL Cu Gap-fill Performance Improvement for 14nm Technology Node

Zhaoqin Zeng, Shanghai Huali Integrated Circuit Corporation
  Enhanced OLT for More Wafer Types in RTP Process

Luo Zhipeng, Applied Materials
  Gate Stack Solution Enabling DRAM Scaling Down to 1x nm Node

Guangyao Shen, Applied Materials China
  Yiin-Kuen Fuh, National Central University

Study of Q-time Effect on Stress Nitride
  Songtao Lv, Applied Materials

Study of PREB Process in FDSOI
  Song Yang, Huali Microelectronics Corporation

Investigation of FDSOI Raised S/D Formation
  Ma Yanfei, Huali Microelectronics Corporation

IDT Structure Optimization Design Based on AlN/Si Substrate for SAW Devices
  Kaixuan Li, Tianjin University of Technology

Titanium Silicide Anneal Process Research for 14nm FinFET Technology

Lan Jiang, HLMC

FDSOI SiGe morphology Optimization on boundary of AA and STI

Jiaqi Hong, HLMC

Optimization of imperfect morphology for SiGe selective epitaxial growth

Yongyue Chen, HLMC

Optimization of the CD uniformity (CDU) in silicon oxide spacer process for 5 nm Fin SAQP Process Flow
  Qingqing Wu, Shanghai IC R&D Center

Dielectric properties of Al2O3 films by pulsed DC magnetron sputtering
  Wen-Yu Cho, National Central University