** to designate keynote talk - 30 min Sponsored by:  
* to designate invite talk - 25 min
  to designate regular talk - 15 min

Symposium Chair: Wenjian Yu
Symposium Co-chairs: Cheng Zhuo and Weikang Qian

Online Conference  
Parallel Symposium Oral Sessions: June 29-July 17, 2020

Session I: Low-Power Design and EDA
** Minimum Energy Operation of Voltage-Scaled Circuits

Hidetoshi Onodera, Kyoto University
* Greedy Dynamic Power (GDP): Power Budgeting and Thermal Management of Multi-Core Systems in the Dark Silicon Era

Hai Wang, University of Electronic Science and Technology of China

Power Oriented CMOL Defect-Tolerant Mapping with Available Nanodevices

Shangluan Xie, Ningbo University
Session II: Reliability-Aware IC Design
* Reliable Design for 3D ICs: From Microarchitecture and Physical Design Perspectives

Yuanqing Cheng, Beihang University

Analysis of ESD Effect and Ionizing Radiation Particles in Gate Oxide

C.-Z. Chen, EtownIP Microelectronics

PCM Waer Leveling AMT Product Team

Chengyu Xu, Chien Wang, Jiangsu Advanced Memory Technology Co. Ltd.
Session III: DTCO Joint session ( II & IX)
** Monolithic 3D enabled Processing-in- SRAM Memory
  Vijaykrishnan Narayanan, Pennsylvania State University
** Reduction of Systematic Defects Through Machine Learning from Design to Fab

James Word, Mentor Graphics
** Full Chip Curvilinear ILT in a Day

Leo Pang, D2S
Session IV: EDA + AI
* Optical Networks-on-Chip (ONoCs): EDA Achievements

Ulf Schlicthmann, Technical University of Munich
* Learning-Based Power Modeling and Optimization for FPGA

Wei Zhang, Hong Kong University of Science and Technology

An Artificial Intelligence Based Defects Auto-Classification System in Semiconductor Manufacturing

Pengfei Wang, Shanghai IC R&D Center

A Neural-Network Approach to Better Diagnosis of Defect Pattern in Wafer Bin Map

Junjun Zhuang, HLMC

Perceptron Algorithm and Its Verilog Design

Wang Kainan, Institute of Information Engineering, CAS
Session V: Advanced IC Design
** A Clock Jitter Tolerant Σ∆ Modulator Employing A Hybrid Loop Filter in CMOS 40nm Technology

Jose Silva-Martinez, Texas A&M University
* Energy-Efficient Inverter-Based Amplifiers: From fundamentals to the state-of-the-arts

Youngcheol Chae, Yonsei University

Towards Optimal Logic Representations for Implication-based Memristive Circuits

Lin Chen, Ningbo University

Timing Violation as Dominant Reason For Failure of Clocked Digital Circuit due to RF Interference in Supply

Shanshan Nong, School of Electronics and Information Technology, Sun Yat-sen University
Session VI: From Physical to System Design
** A Classification Framework Using Incorrectly Labeled Data for Manufacturing Applications

Xin Li, Duke University
* DREAMPlace 2.0: an Open-Source GPU-Accelerated Global and Detailed Placement for Large-Scale VLSI Designs

Yibo Lin, Peking University

A Novel Cellular Array Design Using Quantum-dot Cellular Automata
  Huiming Tian, Ningbo University
  Scalable Multi-Session TCP Offload Engine for Latency-Sensitive Applications
  Jingbo Gao, Fudan University

Conference Poster Session: June 26-July 17, 2020

  Advanced MOSFET Model Based on Artificial Neural Network
  Jiahao Wei, Fudan University
  Hairui Wang, Peking University Shenzhen Graduate School
  Thermal Modeling of Monolithic 3D ICs
  Yuanqing Cheng, Beihang University
  A Compiler Design for a Programmable CNN Accelerator
  Jiadong Qian, Fudan University
  An efficient Digital Frequency calibration scheme oriented High Precision Clock Synchronization technology for Time-triggered Ethernet
  Haiying Yuan, Beijing University of Technology
  A 5.5nW Voltage Reference Circuit
  Kaixuan Du, Peking University
  A high linearity readout integrated circuit for uncooled IR detector
  Chang Liu, Nanjing University
  Wenjie Liang, Tsinghua University