Symposium Chair: Prof. Pingqiang Zhou, Shanghai Tech University, China
| ** | to designate keynote talk - 30 min | |||
| * | to designate invite talk - 25 min | |||
| to designate invite talk - 15 min |
Monday, March 24, 2025 Shanghai International Convention Center
Meeting Room: 3E
Session I: The Future Chip
Session Chair: Pingqiang Zhou, ShanghaiTech University
| 13:00-13:05 | Opening Remarks |
| Pingqiang Zhou, ShanghaiTech University | |
| **13:05-13:35 | Open Source Chip: Achievement and Challenges |
| Yungang Bao, Chinese Academy of Science, Institute of Computing Technology | |
| *13:35-14:00 | How 3D-IC speed-up High Memory Bandwidth AI Chip |
| Brian Li, Cadence Design Systems | |
| *14:00-14:25 | From Placement to Routing: Machine Learning Solutions for Design Rule Violation Forecasting |
| Yu-Guang Chen, National Central University |
Session II: FPGA-enabled Future Computing
Session Chair: Zhufei Chu, Ningbo University
| 14:25-14:40 | Precision Analysis and Hardware Acceleration for Large Scale Quantum Fourier Transformation on Modern FPGAs |
| He Li, Southeast University | |
| 14:40-14:55 | Custom Design of CXL Controller on Intel FPGA R-Tile |
| Chun-Zhang Chen, Peng Cheng Lab | |
| 14:55-15:10 | Verification of PCIe over Electronic and Photonic I/Fs |
| Chun-Zhang Chen, Peng Cheng Lab | |
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| 15:45-17:55 | Poster Session |
Tuesday, March 25, 2025 Shanghai International Convention Center
Meeting Room: 3E
Session III: AI for IC
Session Chair: Yanan Sun, Shanghai Jiao Tong University
| **08:30-09:00 | AI Empowered Radio-Frequency Power Amplifier Design and Modelling |
| Jianguo Ma, Zhongyuan University of Technology | |
| *09:00-09:25 | LLM Enhancement for Secure RTL Generation |
| Yier Jin, University of Science and Technology of China | |
| *09:25-09:50 | Analytical Differentiable Optimization for EDA in the AI Era |
| Rongjian Liang, NVIDIA, USA | |
| 09:50-10:05 | Coffee break |
Session IV: Recent Advances in EDA Technologies
Session Chair: Yu-Guang Chen, National Central University
| *10:05-10:30 | On Automated Generation of Adversarial Camouflage Against Autonomous Driving |
| Yu Li, Zhejiang University | |
| 10:30-10:45 | Enhancing Alliance VLSI Toolchain by Mixed Gate-level Logic Synthesis |
| Zhufei Chu, Ningbo University | |
| 10:45-11:00 | Accelerating the Physical Design of Large FPGAs Through Divide-And-Conquer Methodology |
| Wanzheng Weng, ShanghaiTech University | |
| 11:00-11:15 | A Dynamic Congestion-Aware Analytic Initial Routing Flow for VLSI Designs |
| Lang Feng, Sun Yat-sen University | |
| 11:15-11:30 | Dynamic Noise Sensitivity Based Critical Path Selection |
| Siyu Yun, Zhejiang University | |
| *11:30-11:55 | Genetic Algorithm as a Design Tool for Freeform MEMS Device |
| Chen Wang, University of Leuven | |
| 11:55-13:30 | Lunch Break |
Session V: Computing in Memory
Session Chair: He Li, Southeast University
| *13:30-13:55 | Transforming AI: The Impact of Computing-in-Memory on Future Technologies |
| Tae Hyoung (Tony) Kim, Nanyang Technological University | |
| *13:55-14:20 | Emerging Trends and Advances in Computing-In-Memory: A Software-Hardware Co-Design Perspective |
| Yingjie Qi, Beihang University | |
| 14:20-14:35 | Hop-CIM: An All-Digital Two-level Approximate SRAM-CIM Macro for High Energy-Efficient HNN Acceleration with Data-Aware Early Exit Mechanism |
| Yanan Sun, Shanghai Jiao Tong University | |
| 14:35-14:50 | A Temperature and Process Robust Logarithmic Circuit for CIM Application |
| Ruizhe Sun, Zhejiang University | |
| 14:50-15:05 | Coffee break |
Session VI: Advanced Circuit Design Technologies and Their Applications
Session Chair: Lang Feng, Sun Yat-sen University
| *15:05-15:30 | Cryptographic Failures by Processor Vulnerability |
| Yongqiang Lyu, Tsinghua University | |
| *15:30-15:55 | Neural Rendering Circuits and Systems for Next Generation Graphics |
| Xin Lou, ShanghaiTech University | |
| *15:55-16:20 | ANAS: Approximate Neural Architecture Search via Reinforcement Learning |
| Zheyu Yan, Zhejiang University | |
| 16:20-16:35 | Automatic Partition for Hybrid Stochastic-Binary-Based Circuits |
| Zexi Li, Shanghai Jiao Tong University | |
| Poster Session: | |
| Circuit Design and Snesk Path Current Analysis of 28NM 1T4R RRAM Memory IP | |
| Jianshi Tang, Tsinghua University | |
| LC-VCO With Wide Tuning Range Based On 65nm Process | |
| Lina Huang, Shaoxing University | |
| A Low-Power Passive BLE Wake-up Receiver with Single Sideband(SSB) Backscatter System | |
| Yunhan Gan, Southeast University | |
| RF Switch-LNA Integration for RFFE in 65nm SOI Technology | |
| Ruofan Dai, Shanghai Huahong Grace Semiconductor Manufacturing Corporation | |
| Design of a Line Driver for High-Speed Power Line Communication Applications | |
| Shunxin Xu, Zhejiang University | |
| Circuit Model and Wordline Driver Targeting for Wordline Open Effect in 3D DRAM | |
| Zhixian Pan, Beijing Superstring Academy of Memory Technology | |
| A Temperature Compensating Dynamic Biasing Circuit for A K-Band Driving Amplifier | |
| Hangbiao Li, Southwest China Institute of Electronics Technology | |
| The Design of a Sub-Nanoampere (nA) Level Low-Offset Rail-To-Rail Unity-Gain Op-Amp | |
| Zhifei Feng, Zhejiang University | |
| Improving BEOL Metal Missing by Reducing Antenna Effect for 28HK Metal Gate Process | |
| Zherui Cao, Shanghai Huali Integrated Circuit Co., Ltd | |
| A 10.2-to-14.82-GHz Low-Phase-Noise All-Digital Phase-Locked Loop | |
| Hongsheng Ye, South China University of Technology | |
| Enhanced Floating Random Walk Algorithm for Capacitance Extraction Considering Damage Effects | |
| Bo Wu, Beijing Smartchip Microelectronics Technology Co. Ltd | |
| Accelerated Simulation of Electromigration Based on Equivalent Circuit | |
| Hengyi Zhu, Shanghai Jiao Tong University | |
| Chiplet DFT Solutions for Cross-Die Testing Channels | |
| Zhiyu Li, Sanechips Technology Co., Ltd | |
| A 60GHZ Four-Stage Cascaded LNA for 802.11AD Protocol with 22.3DB Gain and 3.45 Noise Figure | |
| Yi Yao, Tsinghua University | |