Symposium Chair: Prof. Pingqiang Zhou, Shanghai Tech University, China
| ** | to designate keynote talk - 30 min | |||
| * | to designate invite talk - 25 min | |||
| to designate regular talk - 15 min |
Sunday, March 22, 2026, Kerry Hotel Pudong, Shanghai
Meeting Room: Function Room 3
Session I: AI for IC (1)
Session Chair: Pingqiang Zhou
| 13:00-13:05 | Opening Remarks |
| **13:35-14:05 | TBD |
| Ulf Schlichtmann, Technical University of Munich | |
| *14:05-14:30 | Advances in Curvilinear Mask Optimization |
| Bei Yu, The Chinese University of Hong Kong | |
| 14:30-14:55 | Coffee Break |
Session II: AI for IC (2)
Session Chair: Yuzhe Ma
| *15:10-15:35 | Agentic AI for Agile End-to-End SoC Design |
| Tianyu Jia, Peking University | |
| *15:35-16:00 | TBD |
| Qi Sun, Zhejiang University | |
| 16:00-16:15 | Test Program Development using DevOps and AI-assistant coding |
| Biaoxing Gan, Fudan University | |
| 16:15-16:30 | Test Program Development using DevOps and AI-assistant coding |
| Weixiong Li, Teradyne | |
| 16:30-18:00 | Panel Discussion |
Monday, March 23, 2026, Kerry Hotel Pudong, Shanghai
Meeting Room: Function Room 3
Session III: Advanced EDA Technologies
Session Chair: Yanan Sun
| **08:30-09:00 | TBD |
| Wenjian Yu, Tsinghua University | |
| *09:00-09:25 | Simulation and Modeling Methods for Two-Dimensional Field-Effect Transistors |
| Hailong Yao, University of Science and Technology Beijing | |
| *09:25-09:50 | Towards Sustainable and Transparent Benchmarking for Academic Physical Design Research |
| Zhi'ang Wang, Fudan University | |
| 09:50-10:05 | Coffee break |
Session IV: Innovations in Chip Verification and Test
Session Chair: Hailong Yao
| *10:05-10:30 | Challenges and Considerations for Ultra-Large-Scale Full-Chip Power Integrity Signoff |
| Ji Li, Shanghai LEDA Technology | |
| *10:30-10:55 | TBD |
| Runjie Zhang, PHLEXING | |
| *10:55-11:20 | AI for Hardware Formal Verification |
| Hongce Zhang, Hong Kong University of Science and Technology (Guangzhou) | |
| 11:20-11:35 | System Verification of Compute Express Link over Optics towards Large Scale Memory Pooling |
| Xuhui Liu, Peng Cheng Laboratory | |
| 11:35-11:50 | System Interconnect Test on Compute Express Link Using Scalable Memory Development Kit |
| Yue Geng, Peng Cheng Laboratory | |
| 11:50-13:30 | Lunch Break |
Session V: Advanced Circuit Design Technologies and Their Applications
Session Chair: Hongce Zhang
| *13:30-13:55 | TBD |
| Wei Yan, Peking University | |
| 13:55-14:10 | Single-Frequency FBAW-SMR Filter Design for 6G FR3 Band (7.125–8.4 GHz) |
| Xian Ji, IWA SYSTEMS INC | |
| 14:10-14:25 | A Speech Recognition Accelerator Based on Dual-Rail Design with Sensitivity-Aware Allocation |
| Weixuan Wang, Southeast University | |
| 14:25-14:40 | Design of A Universal LVDS-Based 4K@60Hz Video Process Development Platform |
| Yang Cui, Southeast University | |
Session VI: Emerging Design and CAD Technologies
Session Chair: Zhi'ang Wang
| *14:55-15:20 | 2.5D/3D EDA+New Paradigm-Advanced Packaging: Architecting, Physical Implementation, Simulation and Testing |
| Yi Zhao,Zhuhai Silicon Core Carbon Cloud Technology | |
| *15:20-15:45 | TBD |
| Manuel Restituto, Institute of Microelectronics of Seville | |
| 15:45-16:00 | A Performance-driven Digital Computing-in-Memory Compiler with LLM Assisted Analysis Method |
| Wangxi Cai,Zhejiang University | |
| 16:00-16:15 | A Lightweight Pipelined Architecture for CNN Deployment on Edge Devices |
| Ruitong Qiao, Peking University | |
| Poster Session:16:00-18:00 | |
| A Broadband RF Power Detector with High Sensitivity in 65-Nm CMOS | |
| Hangbiao Li, Southwest China Institute of Electronics Technology | |
| AI-Assisted Regression Optimization for UVM-Based IP Verification | |
| Abinaya Senthil, NXP Semiconductor | |
| A Comprehensive Tool for Modeling Non-Ideal Effects in Column-Driver Signal Chain of Micro-LED Displays | |
| Aoran Xu, Peking University | |
| A High-Performance Fully Integrated RF Power Amplifier Output Matching Network Featuring an ESD Discharge Path | |
| Bingsheng Huang, Zhejiang University | |
| Design of a Line Driver for High-Speed Power Line Communication Applications | |
| Shunxin Xu, Zhejiang University | |
| A 240 × 160 18-bit SPAD HDR Imaging Chip Using 3D-Stacked Technology | |
| Langzhi Guo, Nanjing University | |
| An FPGA-Based High-Speed Reconfigurable Accelerator for YOLO | |
| Hanran Gao, Beihang University | |
| A Instruction-Level Dual-core Lockstep RISC-V Processor with Hardware Latent Error Containment | |
| Le Kong, Fudan University | |
| A Three-Stage Gate Driving DC–DC Converter With Ringing Suppression for Automotive Applications | |
| Hang Li, Zhejiang University | |
| A low power Protocol Process Unit for Wireless Sensor Networks with MDT Anti-collision Algorithm | |
| Kaiyue Li, Tsinghua University | |