** to designate keynote talk - 30 min      
* to designate invite talk - 25 min
  to designate regular talk - 20 min

Monday, June 26, 2023 Shanghai International Convention Center
Meeting Room:

Session I: Lithography / Etch joint session (II & III)
Session Chair:
13:30-13:35 Opening Remarks
**13:35-14:05 Etch, Litho, Photo Resists interactions in Patterning
  Allen Chang, JSR
**14:05-14:35 Co-advancing Scaling Techniques and Functionality Enhanced Potential Device Infrastructures
  David Xiao, Shanghai Integrated Circuit R&D Center
**14:35-15:05 An ocean of opportunities in a fast growing market using ASML TWINSCAN systems
  Henri van Helleputte, ASML Netherlands B.V.
15:05-15:30 Coffee Break

Session II: Lithography Materials
Session Chairs: Zhimin Zhu / Xiaoming Ma
15:30-15:50 A Positive-Tone Photosensitive Polyimide Material for Semiconductor Packaging
  Yongqiang Wang, Jinan ShengQuan New Materials Limited
**15:50-16:20 Recent progress of EUV resist development for improving Chemical Stochastic
  Toru Fujimori, FUJIFILM Corporation
*16:20-16:45 From micro to nano, and beyond, --- Measuring Innovations ---
  Zhigang Wang, Hitachi High-Tech Corporation

Tuesday, June 27, 2023 Shanghai International Convention Center
Meeting Room:

Session III: Process and Simulation
Session Chairs: Yuyang Sun / Da Yang
**8:30-9:00 Challenges of the Advanced Lithography for the Next Decade
  Yasin Ekinci, Paul Scherrer Institute
9:00-9:20 Modification of Organic Underlayer by Plasma During Dry Etching and its Effect on the Film Properties
  Soojung Leem, DuPont Electronics & Industrial
*9:20-9:45 CycleGan-based mask diffraction model
  Yijiang Shen, Guangdong University of Technology
9:45-10:05 Illumination optimization for the BEOL DTCO with 45 degree local interconnection
  Xianhe Liu, Fudan University
10:05-10:30 Coffee Break

Session IV: Computational Lithography
Session Chairs: Ken Wu / Yayi Wei
10:30-10:50 Process and tool monitor and diagnosis based on overlay data and modeling
  Yi Tong, Guangdong Greater Bay Area Institute of Integrated Circuit and System
10:50-11:10 The Analysis of Optical Critical Dimension Signal Strength Between 5 nm FinFET and 3 nm CFET Vertical Gate Stacks
  Qi Wang, Fudan University
**11:10-11:40 The Possibility of Using 193 nm Immersion Lithography Process for 5 nm Logic Design Rules
  Qiang Wu, Fudan University
11:40-13:30 Lunch Break

Session V: Next Generation Lithography
Session Chairs: Wei-Min Gao / Motokatsu Imai
13:30-13:50 Enhancement of pattern depth in plasmonic lithography for practical application
  Dandan Han, University of Chinese Academy of Sciences
**13:50-14:20 Performance Improvements on Nanoimprint Tools for Semiconductor Device Manufacturing
  Keita Sakai, Canno Inc.
*14:20-14:45 DUV Mask Writer addressable to 90nm nodes with a Sustainability Profile
  Youngjin Park, Mycronic Co. Ltd.
*14:45-15:10 Patterned wafer defect inspection at advanced technology nodes
  Jinlong Zhu, Huazhong University of Science and Technology
Poster Session:
  Comprehensive optimize 22nm contact correction assisted by rigorous model
  Tongguang Ge, Shanghai Huali Integrated Circuit Corporation
  Study on optical proximity correction method of D-I transition pattern in Metal of 22nm chip
  Wenhao Sun, Shanghai Huali Integrated Circuit Corporation
  Etch model accuracy improvement using SEM image contours
  Ting He, Semiconductor Manufacturing International (Shanghai) Corporation
  Study on inter-layer overlay of stitching lithography technology
  Hongmin Liu, Semiconductor Manufacturing International Corp.
  A Negative-tone Photosensitive Epoxy Material
  Ke Bai, Shandong Shengquan New Materials Co. Ltd.
  New model-based scattering bar local repair method for 2D pattern
  Ge Zhang, Semiconductor Manufacturing International Corporation
  Process window improvement method based on AA
  Xiandi Guo, Shanghai Huali Integrated Circuit Corporation
  Deep-learning based etch model study for DRAM manufacturing
  Lei Wu, ChangXin Memory Technologies, Inc.
  Kissing corner rounding improvement by special OPC
  Jiao Yuan, Semiconductor Manufacturing International Corporation
  A SRAF Method to Improve Process Window in Metal Layer
  Wei Wei, Shanghai Huali Integrated Circuit Corporation
  The Method of CT Overlay and Yield Improvement by Optimizing the Profile of Front Layer
  Zhejun Liu, Shanghai Huali Integrated Circuit Corporation
  Study on-product overlay improvement for immersion lithography
  Guoping Liu, Shanghai Huali Integrated Circuit Corporation
  Line-End Roundness and Voids Improvement of BEOL Metal Layer
  Mudan Wang, Shanghai Huali Integrated Circuit Corporation
  OPC Correction Method Based on Corner to Corner Structure
  Qiguang Zhou, Shanghai Huali Integrated Circuit Corporation
  Layout pattern analysis and coverage evaluation in computational lithography
  Yaobin Feng, Huazhong University of Science and Technology