** to designate keynote talk - 30 min Sponsored by:  
* to designate invite talk - 25 min
  to designate regular talk - 15 min

Symposium Chair: Kafai Lai
Symposium Co-chairs: Linyong (Leo) Pang, Qiang Wu and George Lu

Online Conference  
Parallel Symposium Oral Sessions: June 29-July 17, 2020

Session I: Lithograpy/Etch joint session (II & III)
** DRAM, NAND, and Emerging Memory Technology Update

Jeongdong Choe, TechInsights
** The Law that Guides the Development of Photolithography Technology and the Methodology in the Design of Photolithographic Process
  Qiang Wu, Shanghai IC R&D Center
Session II: Computational Lithography
* Accurate etch modeling with high-volume metrology and deep-learning technology

Wei Yuan, ICRD

Fast and Accurate Machine Learning Inverse Lithography Using Physics Based Feature Maps and Specially Designed DCNN

Xuelong Shi, ICRD

Accurate mask model approaches for wafer hot spot prediction and verification

Young Mog Ham, Photronics

Etch Model Based on Machine Learning

Rui Chen, IMECAS

A Simulation Study for Typical Design Rule Patterns and the Photo Absorption Stochastics and Deffectivity Mpdel in a 5NM Logic Process with EUV Lithography

Yanli Li, ICRD
Parallel Session

Mitigation of microbridging defects in EUV lithography through advanced filtration technologies

Toru Umeda, Nihon Pall Ltd.

Development of 90 nm & 5 nm patterning materials for lithographic technology

Hai Deng, Fudan University
Session III: DTCO Joint session ( II & IX)
** Monolithic 3D enabled Processing-in- SRAM Memory
  Vijaykrishnan Narayanan, Pennsylvania State University
** Reduction of Systematic Defects Through Machine Learning from Design to Fab

James Word, Mentor Graphics
** Full Chip Curvilinear ILT in a Day

Leo Pang, D2S
Session IV: Multiple patterning
* A Study of Image Contrast, Stochastic Defectivity, and Optical Proximity Effect in EUV Photolithographic Process under Typical 5 nm Logic Design Rules

Qiang Wu, ICRD

The topography effect on the lithography patterning control for VLSI fabrication

Dongyu Xu, Huali
Session V: Tool, Mask & Metrology
** Challenge of High Power LPP-EUV Source with Long Collector Mirror Lifetime for Semiconductor HVM

Hakaru Mizaguchi, Gigaphoton
* Line Width and Roughness Measurement of Advanced FinFET Features by Reference Metrology

Mamsami Ikota, Hitachi High Tech

High Speed Wafer Geoemtry on Silicon Wafers Using Wave Front Phase Imaging for Inline Metrology

Jan Gaudestad, Wooptix
Session VI: Process & Material

How to improve' Chemical Stochastic' in EUV lithography ?

Toru Fujimori, Fujifilm Corp.
* Rigorous VASE Data Fitting Ultrathin Film Measurement

Zhimin Zhu, Brewer Science

Conference Poster Session: June 26-July 17, 2020

  Impacts of RTP pyrometer offsets on wafer overlay residue

Lv Jian, HLMC  
  Mix and Match Overlay Improvement of 55nm M1 Layer On Nikon Immersion Scanner
  Ma Yuanzhao, Nikon Precision Shanghai
  MudanWang, HLMC
  Optical Scatterometry Modeling of 5 nm Structures with RCWA Method and Perfectly Matching Layer (PML) Boundary Conditions
  Aihua Yang, Shanghai IC R&D Center
  Xie Weimei, Chen Yanpeng, Yu Shirui, HLMC
  Study of alignment & overlay strategy in 14nm lithography process
  Lulu Lai, HLMC
  Litho Process Optimization to Improve Overlay Measurement in Thick PR Layer
  Jiantao Wang, HLMC
  Effects of Electron Beam on Photo Resist Shrinkage and Critical Dimension in SEM Measurement
  Yuyang Bian, HLMC
  Enlarge Process Window of BSI in DTI Loop :A Novel OPC Approach to Add SRAF
  Qiao Yanhui, HLMC
  Solvement of TEOS residues during 19NAND process
  Fang Ma, Shanghai Huali Microelectronics Corporation
  Critical Dimension Uniformity Improvement of Negative Toned Developing Process for Hole Type Pattern
  Rui-Lin Zhang, Semiconductor Manufacturing International Corp
  Mask fidelity improvement using different MPC techniques
  Mohamed Ramadan, Photronics