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+86.21.6027.8500
English
March 20-22, 2019
Shanghai New International Expo Centre

Qi Wang

VP of Cadence Design Systems Inc. and the CEO of Nanjing Kaiding Electronics Technology Co. Ltd.

Dr. Qi Wang is currently the VP of Cadence Design Systems Inc. and the CEO of Nanjing Kaiding Electronics Technology Co. Ltd., a subsidiary of Cadence. He has over 20 years experience in EDA and held various R&D and marketing positions at Cadence. Prior to his current role, he is the VP and Chief of Staff to the CEO to assist CEO in various management and operation tasks of the company. Prior to that he is the Product Marketing Group Director of the Solutions Marketing group, with a focus on Cadence low power and mixed signal solutions. He is the chief architect of Common Power Format, which was contributed to Si2 and became the industry first open power format in early 2007. He held various positions in international standard organization like Si2 and IEEE. He had more than 20 papers published in various international conferences and journals. He also holds 7 US patents and a recipient of Cadence Outstanding Patent Award in 2010. In 2011, he received the Distinguished Service Award from Si2. Dr. Wang received his Ph.D. degree in Computer Engineering from University of Arizona and his B.S. degree from Shanghai Jiao Tong University.

Speech Abstract:

Presentation Title: AI/ML – Driving Force for Next Generation EDA Innovation

Machine learning and Artificial intelligence is making a profound impact in many applications and industries. Traditionally, EDA is a professional and technology savvy industry which is almost religious to computer algorithms. With the slowing down of Moore’s Law and new technology challenges as the manufacturing technology scaling down to 3nm or lower, the challenges faced by EDA industry are increasing exponentially. Will ML/AI become a new engine for innovation in EDA? Will it work for all problems or just some? Will the dependency on previous data create concerns in data security? The presentation will take some current research work at Cadence as examples to explore the opportunities brought into EDA by AL/ML and how it will benefit the chip designers to address all the new challenges in advanced SoC designs.