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March 20-22, 2019
Shanghai New International Expo Centre

Keynote & Invited Speakers

Keynote & Invited Speakers(2019)

The Floating-Gate Memory—From Concept to Flash Memory to Digital Age
Dr. Simon M. Sze, Honorary Chair Professor, NCTU
     
Dr. Yaoguo (Gary) Ding, Vice President, Intel    
                 
Semiconductor Innovation and Scaling: A Foundry Perspective
Dr. Min Cao, Vice of President, Path-finding, TSMC
     
"In-memory Computing": Accelerating AI Applications
Dr. Evangelos Eleftheriou, Fellow, Neuromorphic Computing, IBM
Sponsored by:
                 
                 
Partial List of Other Confirmed Distinguished CSTIC 2019 Invited Speakers
                 
Accelerating Deep Neural Networks with Analog Memory Devices
Dr. Geoff Burr, IBM
     
Non-volatile Memory for Neuromorphic Computing
Prof. Sangbum Kim, Seoul Natioanl University
   
                 
Towards Efficient AI On-a-chip: A Joint Hardware-algorithm Approach
Prof. Yu Cao, Arizona State University
        Van der Waals Pt/WSe2 Contact for Steep Slope Negative Capacitance and Strong Unipolar p-type Field Effect Transistors
Prof. Yang Chai, Hong Kong Polytechnic University
   
                 
Scaling and Printing Electronics Using Nanomaterials
Prof. Aaron D. Franklin, Duke University
     
AC NEGF simulation: Efficient implementation and application to nanosheet MOSFETs
Prof. Sung-Min Hong, Gwangju Institute of Science and Technology
   
                 
STT-MRAM Materials and Devices
Dr. Guohan Hu, IBM Watson Research Center
     
ReRam for alternative computing architectures
Prof. Khaled N. Salama, UCSD
   
                 
Super steep switching CMOS device technology
Prof. Changhwan Shin, Sungkyunkwan University
     
Steep-Slope Hysteresis-Free Negative-Capacitance 2D Transistors
Prof. Peide Ye, Purdue University
   
                 
Design & Technology Co-optimization for High Performance Mobile SoC Productization
Dr. Jun Yuan, Qualcomm
     
New Understanding of Negative Capacitance Devices for Low-Power Logic Applications
Prof. Qianqian Huang, Peking University
   
                 
  Understanding the negative capacitance in nanoscale by two-dimensional phase field simulations
Cheol Seong Hwang, Seoul National University
             
                 
Novel gap filling BARC with high chemical resistance
Mr. Yuto Hashimoto, Nissan Chemical Corporation
     
High Power LPP-EUV Source with Long Collector Mirror Lifetime for Semiconductor High Volume Manufacturing
Dr. Hakaru Mizoguchi, Gigaphoton Inc.
   
                 
  Advances in IC Mask Synthesis and Tape Out Operations in the era of Machine Learning
Dr. Steffen Schulze, Mentor Graphics
     
Reduction and control of edge placement error at the 5nm node through a holistic approach
Dr. Robert Socha, ASML
   
                 
Advanced Lithography Material Status toward 5nm Node and beyond
Dr. Koichi FUJIWARA, JSR Shanghai Co., Ltd.
     
Pattern fidelity control on EUV via hole towards 5-nm node
Hidetami Yaegashi, Tokyo Electron Limited
   
                 
Multi-beam mask writer MBM-1000
Dr. Hiroshi Matsumoto, NuFlare Technology
     
EUV Lithography optics - current status and outlook
Dr. Dirk Juergens, Carl Zeiss SMT GmbH
   
                 
  TBD
        Evolution of Lithographic Materials Enabling the Semiconductor Industry
Dr. Cheng-Bai Xu, DowDuPont
   
                 
Tailoring Material and Process Variables to Control Planarization Properties at ≤ 7-nm nodes
Daniel M. Sullivan, Brewer Science
     
Study of CD-SEM based and other reference metrologies for line width roughness (LWR) control on EUV photoresist and less than 20nm width materials
Dr. Takeshi Kato, Hitachi High Technologies
   
                 
Boosting computational lithography performance with high speed metrology and machine learning technology
Dr. Gary Zhang, ASML-Brion
     
TBD
Will Conley, ASML-Cymer
   
                 
  HOW CURVILINEAR MASK PATTERNING WILL ENHANCE THE WAFER PROCESS WINDOW: A STUDY USING RIGOROUS WAFER+MASK DUAL SIMULATION
Ryan Pearman, D2S
     
Multi-Beam Mask Writer for Advanced Patterning
Naoya Hayashi, Dai Nippon Printing Co., Ltd.(DNP)
   
                 
  TBD
Kazuyo Morita, Oji Holdings
        TBD
Takahashi, Canon
   
                 
Defectivity Reduction in EUV Lithography Materials using Advanced Filtration Technologies
Rao Varanasi, Pall Corporation
     
Thin Film Characterization for advanced patterning
Dr. Zhimin Zhu, Brewer Science
   
                 
  Modeling and simulation approaches to atomistic control in etch and deposition processes: the role of surface modification and the catalytic nature of hydrogen
Dr. P. L. G. Ventzek, TEL
     
Towards the New Understanding of VHF Plasma Uniformity: Measurements of RF Magnetic Fields and Plasma Conduction Current in VHF Plasma Sources
Dr. Jianping Zhao, TEL
   
                 
  Atomic level surface treatment by down-stream plasma generated radicals
Dr. Xinliang Lu, Mattson Technology
        Single Wafer Clean Challenges and Status
David Wang, ACM
   
                 
  TBD
Kaidong Xu, Leuevn Instrument
     
TBD
David Huang, Pall
   
                 
  TBD
Ying Huang, AMAT
        Advanced Si Etch System for 14nm and beyond
Tomoki Suemasa, Beijing NAURA Microelectronics Equipment Co. Ltd.
   
                 
Cobalt Electrofill for Future Generations of Contacts and Interconnects
Tighe Spurlin, Lam Research
     
Direct Copper Damascene Fill on Cobalt Liner Structures
Lee Brogan, Lam Research
   
                 
Developments of Cu Barrier/liner Materials for 10nm CMOS Technology Node & Beyond
Dr. Xiaoping Shi, Naura
        Low K challenge for 7 and 5nm technology nodes
Dr. Kang Sub Yim, AMAT
   
                 
Advanced Nanoscale Magnetic Tunnel Junctions for Low Power Computing
Prof. Weisheng Zhao, Beihang University
        Advanced Ti-based silicides Ohmic contacts in sub-16/14 nm nodes
Dr. Jun Luo, IMECAS
   
                 
  Alternative metallization for advanced interconnects
Dr. Christoph Adelmann, IMEC
     
Integration Options for Enabling Fully Self Aligned Via
Gayle Murdoch, IMEC
   
                 
TBD
Dr. Ji Chul Yang, SK Hynix
     
The Characteristics of PVA Brushes in Post CMP Cleaning
Prof. Jin-Goo Park, Hanyang University
   
                 
  CMP mechanism of GISI multilevel interconnect
Prof. Yuling Liu, Hebei University of Technology
        Advances in CMP Formulations Technology
Dr. Hongjun Zhou, Versum materials
   
                 
High rate ceria slurry and pad combo solution for bulk oxide CMP
Dr. Jinfeng Wang, Cabot Microelectronics
     
High Dilution Ceria Slurry and Auto Stop Ceria Slurry for Bulk Oxide CMP
Dr. Xiansheng Yin, Anji Microelectronics Technology (Shanghai) Co. Ltd.
   
                 
A Study on the Mechanical Role of Pad Asperities in Chemical-Mechanical Polishing
Prof. Sanha Kim, Korea Advanced Institute of Science and Technology
     
Beyond Planarization, into the Realm of Multifunctional Polishing
Dr. Hong Jin Kim, Globalfoundries
   
                 
Study and Improvement on Tungsten Recess in CMP Process
Dr. Lei Zhang, Shanghai Huali Microelectronics Corporation
     
Opportunities and Challenges of CMP technology for advanced memory manufacturing
Dr. Yukiteru Matsui, Toshiba Memory Corp.
   
                 
Reliability challenges for advanced interconnect systems
Dr. Kristof Croes, IMEC
     
The Hype, Myths, and Realities of Testing 2.5D/3D Integrated Circuits
Prof. Krishnendu Chakrabarty, Duke University
   
                 
  Reliability Verification: Why it is complex, important and beneficial?
Sridhar Srinivasan, Mentor Graphics
        TBD
Gary Ditmer, Lam Research
   
                 
  TBD
Jason Shields, Lam Research
             
                 
  TBD
Dr. Evgeni Gousev, Qualcomm
        TBD
Dr. Victor Zhirnov, SRC
   
                 
How to Successfully Overcome Inflection Points by using the Technology Roadmap methodology
Dr. Paolo A. Gargini, International Roadmap for Devices and Systems (IRDS)
     
TBD
Meng-Fan (Marvin) Chang, National Tsing Hua University
   
                 
  Process Overview of Area-Selective Deposition; Surface-Determined Patterning Technology toward Advanced Nanofabrication
Prof. WooHee Kim, Jeonbuk National University
     
Hybrid Solid State Chemoresistive and Fluctuation-Enhanced Gas Sensors: Exhaled Breath and Indoor Air Analysis
Prof. Lars Österlund, Uppsala University
   
                 
A novel gate junction design for low noise Si Nanowire ISFET Sensors
Prof. Zhen Zhang, Uppsala University
     
Chemical and Biological Sensing with Hybrid Plasmonic-Photonic Crystal Nanomaterials
Prof. Alan Xiaolong Wang, Oregon State University
   
                 
Analog Resistive Switching Memory for Neural-Network Processing Unit
Prof. Bin Gao, Hsinghua University
     
Manufacturing Technology of Phase Change Memory (PcRAM) for AI/IoT and Smart Society
Dr. KouKou Suu, ULVAC
   
                 
AI: From Deep Learning to In-Memory Computing
Hsiang-Lan Lung, Macronix
     
The implementation of semiconductor based biosensors into Point of Need systems for the automatized analysis of complex samples
Andreas Morschhauser, Fraunhofer ENAS
   
                 
The Life of SPICE as A Transient Circuit Simulator
Prof. Chung-Kuan Cheng, UC San Diego
     
Edge Computing
for Intelligent Healthcare
Prof. X. Sharon Hu, University of Notre Dame
   
                 
TBD
Prof. Xin Li, Duke University
     
DTCO is the New Moore’s Law for Advanced Logic and Memory
Dr. Victor Moroz, Synopsys Inc.
   
                 

TBD
Prof. Lei He, UC Los Angeles
     
Not your father’s timing anymore - novel approaches to timing of digital circuits
Prof. Ulf Schlicthmann, Technical University of Munich
   
                 
Computing-in-Memory for Binary Neural Networks
Prof. Shimeng Yu, Georgia Institute of Technology
        TBD
Prof. Xuan Zeng, Fudan University
   
                 
Dadu - Processor Design for Robot
Prof. Yinhe Han, Institute of Computing Technology, Chinese Academy of Science
     
Design Automation of Digital Microfluidic Biochips
Prof. Krishnendu Chakrabarty, Duke University
   
                 
Accelerate Analog Circuit Simulation
Senhua Dong, Huada Emprean Inc.
     
A 1μw-to-100μw Output Range Boost DC-DC with Pseudo Open Loop Structure and Power Efficient Ring Oscillator for Wireless Energy Harvesting
Prof. Le Ye, Peking University
   
                 
  TBD
Dr. Davids Wu, Horizon Shanghai IC Design Center