Various emerging non-volatile memory (NVM) technologies, such as STTRAM, PCM, RRAM, have been proposed as candidates for future memory hierarchy design. These emerging NVMs have advantages of high density, zero standby power, fast access speed, non-volatility, which are potential to mitigate the well-known “Memory Wall” problem. In order to achieve high performance, low power consumption, and high reliability memory hierarchy design, we explore these emerging NVMs in different levels. First, the characters of these emerging NVMs are studied in the device level. At the same time, the impact of process variation is analyzed, in respect of access timing and energy consumption. Then, to select proper NVM technologies for different memory specs, the circuit level design issues are discussed, which include a common method of modeling for cell array and peripheral circuitry and related design problems, such as read/write disturbance, thermal fluctuation, sneak current in cross-bar structure, etc. At last, we introduce how to improve the architecture of a traditional memory hierarchy to facilitate the adoption of these emerging. The exploration will cover many interesting topics such as hybrid memory, wear leveling and write-intensity reduction, MLC optimization, secure storage, etc.
Who Should Attend?
If you (students, engineers, and managers) are involved with any aspect of analysis or design for high performance, low power, and reliable memory, you should attend this course. This lecture will cover interesting topics in device, circuit, architecture, and system level for various layers of memory hierarchy design in both high performance and embedded systems. It is equally suited for R&D professionals and scientists. You will receive more than 200 pages of handouts from reference books and frontier research papers.
• Introduction: memory hierarchy in computing systems
• “Memory Wall” – limitations of traditional memory technologies
• Overview of traditional nonvolatile memories (NVMs)
• Emerging NVMs vs. traditional memory technologies
• Who are involved in the community of emerging NVMs?
• Overview of Spin-Torque-Transfer RAM (STT-RAM) technology
• Overview of Phase Change Memory (PCM) technology
• Overview of Resistive random-access memory (ReRAM) technology
• Device level design tradeoff: latency, energy, or retention time?
• Non-deterministic characters of emerging NVMs
• Error control in the device (storage cell) level
• How to select proper NVM technologies in the memory hierarchy?
• Overview of NVM circuit design
• MOS-accessed structure vs. cross-point structure
• Memory array organization, routing, and optimization
• Different data sensing modes
• Design issues in cross-point structure based NVMs
• Process variations in the circuit design
• “NVSim: a Circuit-Level Performance, Energy, and Area Model for Emerging”
• Opportunities and Challenges in architecture design of NVMs
• High performance and low power STT-RAM on-chip memory architecture
• Exploring the Vulnerability of CMPs to Soft Errors with 3D Stacked STT-RAM Cache
• PCM based main memory architecture
• Performance and Lifetime optimization for PCM based main memory
• Data security: a new challenge in NVM main memory
• Employing NVM as storage: a hybrid PCM+NAND flash approach
• Checkpoint and NV processor architectures
• Quick review of system level research topics for emerging NVMs
Dr. Guangyu Sun is an assistant professor of Center for Energy-efficient Computing and Applications (CECA) at Peking University. He received his B.S. and M.S degrees from Tsinghua University, Beijing, in 2003 and 2006, respectively. He received his Ph.D. degree in Computer Science from the Pennsylvania State University in 2011. Dr. Sun received the 2012 EDAA outstanding dissertation award for his Ph.D. thesis titled “Exploring Memory Hierarchy Design with Emerging Memory Technologies”. His research interests include computer architecture, VLSI Design, and electronic design automation (EDA). He has published 40+ journals and refereed conference papers and one book in these areas. He is serving as PI on one NSFC young research grant and one industry grant supported by AMD and Co-PI on one National High Technology Research and Development Program ("863"Program). His research work on memory architecture/system for Big Data is also supported by Baidu. Dr. Sun is an active volunteer in the communities of computer architecture, VLSI, and design automation. He has been serving as a program committee member for many conferences in these areas, including DAC, DATE, ASP-DAC, GLSVLSI, VLSID, and NAS. He served as the local arrangement chair and in TPC for ISLPED 2013. He has also served as a peer reviewer and technical referee for several journals, which include IEEE Micro, IEEE TVLSI, IEEE TCAD, etc. Guangyu Sun is a member of CCF and IEEE.
JY Zhang SEMI China