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Symposium I: Device Engineering and Technology

(** to designate keynote talk, * to designate invite talk)


Sunday, March 13, 2016 Shanghai International Convention Center

Meeting Room3B


Session I: Memory Technology - I

Session Chairs: Ru Huang, Huaqiang Wu



Memory Devices in Computing

Chung Lam, IBM



The Outlook for New Memory Technology

Gary Bronner, Rambus



Memristor Mates Enable Memory and Neuromorphic Applications

Jianhua Joshua Yang, University of Massachusetts




Future Brain-like Computing with Non-volatile Memory Device

Yu Hao, Nanyang Technological University



Coffee Break


Session II: Memory Technology - II
Session Chair: Huaqiang Wu




Zhitang Song, SIMS CAS



DRAM Failures in the field:  An update on Row Hammer

Barbara P Aichinger, FuturePlus Systems



Applying Optimal Design of Experiment in Reversed Self-aligned

Contact Etch Of NOR Flash for Profile Performance Improvement

Erhu Zheng, SMIC



Poster Session:

Location: Foyer of Yangtze River Hall


Coffee Break

An accurate scalable model for 700V LDMOS

Pingliang Li, HHGrace



Characterization FinFET Device Layout Dependent Effect

Xinyun Xie, SMIC



Improved NBTI Characteristic of HKMG FinFET with Thermal Oxidized

Interlayer and Post Interlayer Anneal

Xin He, SMIC



Study on Different Abrasives Effect in Sapphire Chemical-Mechanical


Xiaohua Zhu, Jiangsu Tianheng Nanometer technology Co.,Ltd




Sapphire roughness CMP process control technology

Ding Li, Jiangsu Tianheng Nanometer Technology Co.,Ltd



Process conditions affected chemical mechanical polishing (CMP)

 on sapphire

Rongrong Qin, Jiangsu Tianheng Nanometer Technology Co.,Ltd



The production and application of Nanoscale materials silica

Zhou Zheng, Jiangsu Tianheng Nanometer technology Co.,LTd



A High-Fill-Factor SPAD Array Cell With A Shared Deep N-Well

Yang Huang, Nanjing University of Posts and Telecommunications



Development on High-precision Microelectronic Assembly

Gary Chen, Suzhou Etron Electronics Co. Ltd.



Resolving Plasma Induced Damage for A CMOS Embedded-OTP


Xiaobo Duan, SMIC



Impacts of Random Telegraph Noise (RTN) on the Energy-delay

Tradeoffs of  Logic Circuits

Yang Zhang, Peking University



Monday, March 14, 2016  Shanghai International Convention Center

Meeting Room: 3B

Session III: Device Reliability and Noise Characteristics

Session Chair: Huilong Zhu



Low frequency noise and fin width study of Silicon passivated Germanium


Alberto Vinicius de Oliveira, IMEC, University of Sao Paulo




Compact Modeling of Junction Failure in Semiconductor Devices

Subject to Electrostatic Discharge Stresses

Juin J. Liou, University of Central Florida



Engineering Graphene for Transistors and Interconnects

Moon-Ho Ham, Gwangju Institute of Science and Technology



Coffee Break


Session IV: Novel Solid State Devices

Session Chair: Cor Claeys




CMOS Device Benchmarks and Transition-Metal Dichalcogenide Device

Hitoshi Wakabayashi, Tokyo Institute of Technology



Flexible 2D Semiconducting Electronics

Sunkook Kim, Kyung Hee University



SiGe/Si Tunnel FETs

Qingtai Zhao, Peter Grünberg Institute



The Effects of Materials and Process on the Electrical Characteristics

of Tunneling FETs

Changhwan Choi, Hanyang Universiy



Lunch Break


Session V: Advanced Device and Process Technology

Session chair: Hong Wu



Gate and source/drain engineering in Ge device technology

Ming Li, Peking University



A Study of Narrow Transistor Layout Proximity Effects for 28nm

POLY/SION Logic Technology

Ruoyuan Li, SMIC



Impact of STI stress on 40-nm Dogbone Layout n-MOSFETs

Wang Liu, ShangHai Research Institute of MicroElectronics (SHRIME),

Peking University



Contact Resistance between Graphene and Metal

Ce Yang, Peking University



A New Extraction Method of Parasitic Resistance for Poly-Connected MOSFETs

Haohua Ye, SMIC