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Symposium II:Lithography and Patterning 

(** to designate keynote talk, * to designate invite talk)

  

Sunday, March 13, 2016 Shanghai International Convention Center

 

Joint Session: Symposium II and Symposium III-Lithography/Etch joint session
Meeting Room
3H+3I+3J

Session Chairs: Kafai Lai/Ying Zhang

 

13:30-13:35

Opening Remarks

Kafai Lai / Ying Zhang

 

**13:35-14:05

Moore's Law: No End in Sight

Vivek Singh, Intel

 

**14:05-14:35

Atomic Level Precision Materials Engineering

Peter Loewenhardt, Applied Materials

 

**14:35-15:05

 

Development of 250W EUV light source for HVM  lithography

Mizoguchi, Giaphoton

 

**15:05-15:35

Materials Innovation for Cost-Effective Lithography

Ralph Dammel, EMD / AZ

 

15:35-15:50

Coffee Break

 

Session II: Computational Lithography
Meeting Room: 3rd Floor Yellow River Hall
Session Chairs: Yayi Wei / Shiyuan Liu

 

*15:50-16:10

Impact of photomask shape uncertainties on computational lithography

Edmund Lam, HKU

 

*16:10-16:30

Latest Progress of Model-based Mask Data Preparation for OPC and ILT at

10nm Node and Beyond

Leo Pang,D2S

 

16:30-16:45

A Simulation Study on Two-Dimensional Patterns with Different Post-OPC

Mask Variations

Qiang Wu, SMIC

 

16:45-17:00

Investigation of Chemical Effects in Lithography

Zhimin Zhu, Brewser Science

 

17:00-17:15

Pattern Displacement Caused by OPC Model

Yibin Huang, SMIC

 

 

 

 

Poster Session:

Location: Foyer of Yangtze River Hall

 

Coffee Break

The comparison of the effectiveness of model-based SRAFs and rule-based

SRAFs

Yaojun Du, SMIC

 

 

OPC Convergence Improvement by Matrix OPC Solver on High MEEF Contact

Layer

Wanjuan Zhang, SMIC

 

 

Building block modular recipes for productivity improvement in modern IC  manufacturing flows

Xiaodong Meng, Synopsys Inc

 

 

Sub-Resolution-Assist-Feature Placement study to dense patterns in advanced lithography process

Quan Chen, HLMC

 

 

Metal layer OPC repair flow for 28nm node and beyond

Dan Wang, HLMC

 

 

Corner SRAF Study for CT DOF Enhancement in 28nm Technology Node

Binjie Jiang, HLMC

 

 

The Alignment Performance Study for the Gate Layer in FinFet Processes

Xuan Li, SMIC

 

 

Study of Square Via Fragments in Model Base OPC

Yanpeng Chen, HLMC

 

 

Simulation Studies and Improve Methods for Substrate Reflection Caused

 Issues in Implant Layers for 28nm Node and Beyond

Yueyu Zhang, HLMC

 

 

RET Selection on 14nm Contact Layer

Jinhua Pei, SMIC

 

 

Investigation into PR profile representation through method of OVL focus subtraction based on a case of Overlay AEI-ADI offset on contact layer of advanced technology node

Guogui Deng, SMIC

 

 

Study of via layer overlay control in BEOL trench-first approach

Bin Xing, SMIC

 

 

SELF-ALIGNED DOUBLE PATTERNING (SADP) PROCESS EVEN-ODD UNIFORMITY IMPROVEMENT

Huayong Hu, SMIC

Single Layer Space Patterning in Si Trench

Jiaoyao Liu, SMIC

 

 

Monday, March 14, 2016  Shanghai International Convention Center

Joint Session: Symposium II and Symposium XI-DTCO Joint session

 Meeting Room: 3H+3I+3J

Session Chairs: Leo Pang / Yiyu Shi

 

8:30-8:35

Opening Remarks

Leo Pang / Yiyu Shi

 

**8:35-9:05

Nanolithography and Design Technology Co-optimization in Extreme Scaling 

David Pan, UT Austin

 

**9:05-9:35

Wearable &  Implantable Medical application – a  challenge to integrated

 RF transceiver design 

Zhihua Wang, Tsinghua University

 

**9:35-10:05

The Next Frontier in IC Design: Determining (and Optimizing) Robustness

and Resilience of Integrated Circuits and Systems

Ulf Schlichtmann, Technical University of Munich

 

10:05-10:20

Coffee Break

 

Session IV: MEMS, Mask  & Metrology

Meeting Room: 3rd Floor Yellow River Hall

Session Chairs: Motokatsu Imai/Qiang Wu

 

**10:20-10:50

 

*10:50-11:10

Development history and future of electron beam mask writers

Kiyoshi Hattori, NuFlare

MEMS’s technology trend

Chiaki Kato, Tohoku university

 

*11:10-11:30

Advanced CD-SEM metrology for Edge Placement Error (EPE) control

 at the 15 nm node and beyond

Takeshi Kato, Hitachi HiTec

 

11:30-11:45

Lithography technology and Trends for Advanced Packaging

PIZZAGALLI Amandine, Yole Développement

 

11:45-12:00

Application of CDU Master for 40-nm Critical Layer CD Control: Strategies and Results

Ma Yuanzhao, Nikon Precision Shanghai

 

12:00-13:30

Lunch Break

 

Session V: Multiple patterning

Meeting Room: 3rd Floor Yellow River Hall

Session chairs: Wanh Yueh /  Zhimin Zhu

 

**13:30-14:00

Moore or Less?  The Map Grows Increasingly Complex as Materials

 and Processes Abound

Peter Trefonas, DOW Chemicals

 

*14:00-14:20

Pattern Fidelity control in Multi-patterning towards 7nm node

Hidetami Yaegashi ,TEL

 

14:20-14:35

DTCO Exploration on the 14nm Double Patterning

Yang Qing, SMIC

 

*14:35-14:55

Effective solution for the 14nm node multiple patterning lithography

Lixian Yu, CAS

 

14:55-15:10

A STUDY OF DIFFRACTION LIMITATION AND MINIMUM RUN LENGTH FOR IMMERSION LITHOGRAPHY

Chang Liu, SMIC

 

15:10-15:25

Nikon 207 CDP function evaluation and application study

Wang Hui, HH Grace

 

15:25-15:40

Coffee Break

 

Session VI: Process & Material

Meeting Room: 3rd Floor Yellow River Hall

Session chairs: Gyomei Shiba / Hai Deng

 

**15:40-16:10

HVM materials for Sub-10nm nodes

Wang Yueh, Intel

 

*16:10-16:30

Dry Development Rinse Process (DDRP) and Material (DDRM)

Rikimaru Sakamoto, Nissan Chemicals

 

*16:30-16:50

Design Technology Co-optimization for N14 Metal1 Layer

Xiaojing Su, Yingli Duan, CAS

 

16:50-17:05

A non-chemically amplified positive-tone i-line photoresistfor

high resolution patterning

Liyuan Wang, Beijing Normal University

 

17:05-17:20

 

Study on immersion defectivity of hole-layer patterns in advanced nodes

Xiliang Liu, SMIC

 

    

 

 

 

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