Keynote & Invited Speakers(2016)
Plenary Session
Qing Chu,Vice President,Huawei Technologies Co., Ltd.
Confirmed Invited Speakers
** Keynote Speech * Invited Speech
Symposium I: Device Engineering and Technology
**Gary Bronner,Vice President, Rambus
The Outlook for New Memory Technology
*Changhwan Choi, Associate Professor, Hanyang Universiy
The Effects of Materials and Process on the Electrical Characteristics of Tunneling FETs
*Moon-Ho Ham, Professor, Gwangju Institute of Science and Technology
Engineering Graphene for Transistors and Interconnects
*Yu Hao, Professor, Nanyang Technological University
Future Brain-like Computing with Non-volatile Memory Device
*Jan Hoentschel, GLOBALFOUNDRIES
*Sunkook Kim, Professor, Kyung Hee University
Flexible 2D Semiconducting Electronics
**Chung Lam,DE and Manager, IBM, USA
Memory Devices in Computing
**Juin J. Liou, Professor, University of Central Florida
Compact Modeling of Junction Failure in Semiconductor Devices Subject to
Electrostatic Discharge Stresses
*Ming Li, Peking University
Gate and source/drain engineering in Ge device technology
*Zhitang Song, SIMS CAS
**Hitoshi Wakabayashi, Tokyo Institute of Technology
CMOS Device Benchmarks and Transition-Metal Dichalcogenide Device
**Jianhua Joshua Yang, Professor, University of Massachusetts
Memristor Mates enable memory and neuromorphic applications
*Qingtai Zhao, Peter Grünberg Institute
SiGe/Si Tunnel FETs
Symposium II: Lithography and Patterning
**Vivek Singh, Director, Fellow,Intel
Moore's Law: No End in Sight
**Mizoguchi, CTO, Gigaphoton
Development of 250W EUV light source for HVM lithography
**David Pan, Professor, U Texas at Austin
Nanolithography and Design Technology Co-optimization in Extreme Scaling
*Edmund Lam, Professor, HKU
Impact of photomask shape uncertainties on computational lithography
*Leo Pang, VP, D2S
Latest Progress of Model-based Mask Data Preparation for OPC and ILT at 10nm Node and Beyond
**Wang Yueh, Principal Engineer, Intel
HVM materials for Sub-10nm nodes
**Peter Trefonas, Corporate Fellow, Dow Chemical
Moore or Less? The Map Grows Increasingly Complex as Materials and Processes Abound
*Rikimaru Sakamoto, R&D Manager, Nissan Chemical Industries, LTD.
Dry Development Rinse Process (DDRP) and Material (DDRM)
*Takeshi Kato, Senior Engineer, Hitachi High-Technologies Corporation
Advanced CD-SEM metrology for Edge Placement Error (EPE) control at the15 nm node and beyond
*Lixian Yu, Research staff member, Institute of Microelectronics, CAS
Layout Decomposition for MPT and Lithography Simulation
*Xiaojing Su, Yingli Duan, Research staff member, Institute of Microelectronics, CAS
Design technology co-optimization for N14 Metal1 Layer
**Peter Loewenhardt, VP, Applied Material, USA
Atomic Level Engineering
**Ulf Schlichtmann, Professor, Technical University of Munich
The Next Frontier in IC Design: Determining (and Optimizing) Robustness and Resilience of
Integrated Circuits and Systems
**Zhihua Wang, Professor of Electronic Engineering, Deputy Director of the Institute of Microelectronics, Tsinghua University,
Wearable & Implantable Medical application – a challenge to integrated RF transceiver design
**Ralph Dammel, EMD
Materials Innovation for Cost-Effective Lithography
*Chiaki Kato, Tohoku University
MEMS’s technology trend
*Hidetami Yaegashi, Senior member of technical staff, TEL
Pattern Fidelity control in Multi-patterning towards 7nm node
**Kiyoshi Hattori, Director, NuFalre
Development history and future of electron beam mask writers
Symposium III: Dry & Wet Etch and Cleaning
*Rich Wise, Managing Director, Lam Research, USA
Patterning Technology Inflections for the 10nm, 7nm and 5nm Logic Nodes
**Peter Loewenhardt, VP, Applied Materials, USA
Atomic Level Engineering
*Steven Scheer, Senior Manager, TEL
Patterning Challenges for N7 and Beyond
*Leonid Dorf, Senior MTS, Applied Materials, USA
Low Electron Temperature Etch Chamber (LETEC) for Atomic Precision Etching
*Maxime Darnon, Professor, Université de Sherbrooke, Canada
Plasma etching for High Efficiency Solar Cells fabrication
*Marc Zelsmann, Research Scientist, CNRS, France
A route for industry-compatible DSA of high-chi PS-PDMS block copolymers
*Shenjian Liu, Managing Director and deputy general manager, AMEC,China
Inductive Coupled Plasma Etch Development for 10nm and Beyond Technology Node
*Dr. Peter Ventzek, TEL
Control of Atomic Layer Reactions for Plasma Processing
*Dr. Jun Lin, Tokyo Electron Yamanashi Ltd.
Advanced manufacturing technology: gaseous chemical oxide removal
**Vivek Singh, Director, Fellow, Intel
Moore's Law: No End in Sight
**Mizoguchi, CTO, Gigaphoton
Development of 250W EUV light source for HVM lithography
**Ralph Dammel, EMD
Materials Innovation for Cost-Effective Lithography
**Dr.Chris Penny, Snr Engineer, IBM
Challenges in BEOL (Back End of Line) Cu Integration at the 7nm Node and Beyond
*Dr.Tae-gon Kim, Sr. researcher,Advanced film characterization & 3 dimensional structure characterization, IMEC
Metrology challenges in advanced semiconductor technologies
*Dr.Victor Zhirnov, Chief Scientist,Semiconductor Research Corporation
Scaling Limits of Nanoionic Devices
*Mr.Hao Deng, DCVD Manager, TD-SMIC
New applications and challenges of dielectric films at 14nm FinFET technology and beyond
*Dr.Jingmei Liang, Technology Director, DSM, CVD, AMAT
Flowable oxide: N10 STI Gapfill Challenges
*Dr.Xinyu Fu, Senior Manager of process engineering, MDP, AMAT
A Conformal Low Resistivity Fluorine Free Tungsten for FINFET Metal Gate and 3D Memory Applications
*Dr.Natalia Doubina, Snr process engineer, ECP, Lam Research
Application of Cobalt Electroplating for IC Interconnects
*Dr.Mikhail Baklanov, Principle Scientiest, IMEC
Innovative solutions for integration of ultralow-k materials for 10 nm technology nodes and beyond
*Yanqing Wu, Professor, HUST (Huazhong University of Science & Technology)
High Performance Electronics Based on Novel Two Dimensional Materials
*Peter M. ZAGWIJN, Senior Technical Product Manager, ASM International N.V.
ALD Nanolayers for Novel More than Moore Devices
**Zhenqiang Ma, Professor, University of Wisconsin at Madison, USA
Radio-Frequency Flexible and Stretchable Electronics
**Ning Cheng, Principal Engineer, Altera Corp.
Future FPGA - application, challenges and technology enablement
**Dr. Min-Hwa Chi, Sr. VP, SMIC
FinFET technology: Overview ans status at 14nm node and beyond
**Dr. S.V. Babu, Professor, Clarkson University
Mitigation of corrosion challenges for barrier films at advanced nodes
*Dr. JH Han, Senior Member of Technical Staff, Global Foundries
Chemical Mechanical Polishing Innovation as a Key Technology for sub-10nm Logic Device
*Dr. Jin-Goo Park, Professor, Hanyang University
Adsorption and removal of BTA during Cu CMP and post Cu CMP cleaning
*Dr. Yufei Chen, Distinguished Member of Technical Staff, Applied Materials
Chemical Mechanical Cleaning for CMP Defect Reduction
*Dr. David Huang, Senior Technology Director, Pall
CMP Defect Reduction using Advanced Filtration Technology
*Junzhu Cao, Manager, SMIC
Copper CMP Dendrite Defect Investigation
*Dr. Charles Lin, Director, Dow Chemical
CMP consumable technology and solution addressing 28nm and beyond logic device CMP process challenges
*Jack Fong, Global Application Manager, Cabot Microelectronics
Advancement of Systematic Thinking to Solutions for CMP Applications: "One or More?"
*Dr. Song-Yuan Chang, Sr. VP, Uwiz
Flexible Solutions for Cu Interconnect Planarization and Post Planarization Cleaning
*Elbert Chou, Managing Director, Kinik
A Novel Platform for Next Generation Pad Conditioner and Performance
*Dr. YuChun Wang,Anji Microelectronics
Driving topography down to perfection by slurry foremulation design and cmp process
*Chao-Chang Chen, Professor, Taiwan University of Science and Technology
Study on CMP of Glass Wafer with SiO2 Based Slurry for Trench-Glass-Via Interposer
*Hong Lei, Professor, Research Center of Nano-science and Nano-technology,Shanghai University
PREPARATION OF MG-DOPED COLLOIDAL SILICA ABRASIVE AND ITS CHEMICAL MECHANICAL POLISHING PERFORMANCES ON SILICON WAFER
*Zhaoyun Tang, IMECAS/XMC
Intergration and Devices for 3D-Nand
*Jing Xu, Institute of Microelectronics of Chinese Academy of Sciences
Back Gate Recovery for FDSOI Devices
**Dr.Chris Penny, Snr Engineer, IBM
Challenges in BEOL (Back End of Line) Cu Integration at the 7nm Node and Beyond
*Dr.Victor Zhirnov, Chief Scientist, Semiconductor Research Corporation
Scaling Limits of Nanoionic Devices
**Zhenqiang Ma, Professor, University of Wisconsin at Madison, USA
Radio-Frequency Flexible and Stretchable Electronics
**Ning Cheng, Principal Engineer, Altera Corp.
Future FPGA - application, challenges and technology enablement
**Dr. Min-Hwa Chi, Sr. VP, SMIC
FinFET technology: Overview ans status at 14nm node and beyond
**Tan Boo Wei, Group Engineering Manager, R&D Department, Carsem Semiconductor
Automotive QFN Packaging Solution
**Yifan Guo, VP, ASE Shanghai
Advance in Semiconductor Packaging Technologies for IOT
*Herb Huang, Sr. Director of Technology Development in 3DIC and Sensors, SMIC
Prospectus of Wafer Level 3D System Integration and Packaging Solutions beyond TSV
**John Yuanlin Xie, Director, Packaging Technology Research and Development, Altera Corp., San Jose, CA
Roadmap towards TSV-Free 2.5D Integration
**Daquan Yu, VP Technology, Tianshui Huatian
Development of 3D WLCSP Using Vertical Via Last TSV Technology
**YB Lin, Director, JCET
MIS
*Mark Huang, CTO, Speed
Development of Fingerprint Sensor Module Assembly
*Dr. Dongkai Shangguan, CMO, StatschippaC
Advanced Packaging Technologies for System Integration
**Dr.Daniel Shi, Director, ASTRI
3D Packaging for Power Electronics Application
*Dr.Jianwen Li, VP Technology, SJSemi
*M.L. Huang, Professor, Dalian University of Technology
Dominant effect of diffusion anisotropy in β-Sn grain on electromigration behavior of SnAgCu solder bumps
**Dr. Ken Lee, CTO, SIMMTECH
Form Factor and Cost-Driven Advanced Package Substrates for Mobile and IoT Applications
**John H. Lau, Ph.D., P.E., IEEE Fellow, ASME Fellow, IMAPS Fellow, ASM Pacific Technology
Patent issues of embedded fan-out wafer/panel level packaging
*Prof. C.P. Wong, Professor, The Chinese University of Hong Kong
Supercapcitor Materials for Energy Storage Applications
*Prof. Ricky Lee, Professor, The Hong Kong University of Science and Technology
Bridging the Gap between the Joint and the Board Level Tests for the Evaluation of Pad Cratering
*Johan Liu, Shanghai University, Chalmers University of Technology
2D Heat Dissipation Materials for Microelectronics Cooling Applications
*Prof. K. Suganuma, Professor, Osaka University
Low Temperature Interconnection for Two PE; Printed and Power Electronics
*Prof K. W. Paik, Professor, KAIST
Anisotropic Conductive Films (ACFs) Interconnection Technology for Wearable Electronics Applications
*Takeshi Mori, Sumitomo Bakelite Co., Ltd.
Epoxy molding compound for Fingerprint Sensor
**Adit Singh, Professor of Auburn University, US,IEEE Fellow
Adaptive Testing: Addressing the “Zero Defect” IC Quality Challenge
*Ingo Schulmeyer, Carl Zeiss Microscopy GmbH, Germany
Improved failure analysis of electronic packages by combining x-ray- and scanning electron microscopy
*Barry Linder, Research Staff Member,IBM T. J. Watson Research Center
Combined Ramp Voltage Stress and Constant Voltage Stress for Reliability Modeling from Individual devices to Complete Packaged Chips
*Harry H. Chen, Research Scientist, MediaTek
Upstream data analytics to optimize system test
*Jian Fu Zhang, Professor, Liverpool John Moores University
Defects for Random Telegraph Noise and Negative Bias Temperature Instability
*Dr. Hongsik Jeong, Professor, Yonsei University
High Density PCM Technology
*Dr. Kuan-Neng Chen, Professor, National Chiao Tung University
Research Advances of Low Temperature Bonding Technology in 3D Integration and Heterogeneous Integration
*Dr. Yi-Chia Chou, Professor, National Chiao Tung University
Forming new silicide heterostructures in semiconductor nanowires
*Dr. Sung Hyun Jo, Senior Fellow, Crossbar
Resistive RAM: Beyond Emerging Memory Technology
*Dr. Jung Heon Lee, Professor, Sungkyunkwan University (SKKU)
Ultra-stable Gold Nanoparticles with DNA Directed Biological Functionality
*Dr. Chul-Ho Lee, Professor, Korea University
Optoelectronics based on Two-dimensional Semiconductor Heterostructures
*Dr. Dohun Kim, Professor, Yonsei University
Recent progress in developing semiconductor quantum dot based quantum bits
*Dr. Wenqi Zhang, Director, National Center for Advanced Packaging (NCAP)
Optical receiver with Si photonics for high speed optical communication
*Dr. Chien-Hung Lin, Director, Kingyoup Optronics
Submicron Polymer Temporary Bonding with Ultra-Fast Laser Ablation Application in 3D Semiconductor Package
*Masaaki Kuzuhara, Professor, Graduate School of Engineering, University of Fukui
GaN-based Heterojunction FETs for Power Applications
*Yasuyuki Miyamoto, Professor, Department of Physical Electronics, Tokyo Institute of Technology
Steep slope devices with InGaAs channel for post Si CMOS application
*Dr. SangBum Kim, Research Staff Member, IBM T.J. Watson Research Center.
Neuromorphic computing based on emerging non- volatile memory devices
*Dr. Chung-Hsun Lin, Device Engineering, Advanced Technology Development, GLOBALFOUNDRIES
Advanced CMOS Technology Development at GLOBALFOUNDRIES
*Dr. Zhiqiang Wei, Chief Engineer, Panasonic
Projecting the Reliability for 40 nm Embedded ReRAM and beyond
*Dr. Carlo Reita, Director, Nanoelectronics Technical Marketing and Strategy, CEA LETI
Solution for nanoelectronics beyond the 7nm node
*Dr. Edward Y. Chang, Dean, International Colledge of Semiconductor Technology, National Chiao Tung University
Study On The Electrical Characteristics of In Situ PEALD-Passivated HfO2/In0.53Ga0.47As MOSCAP and MOSFET Structures
*Dr. Jihwan An, Professor, Seoul National University of Science and Technology
Application of ALD to Energy Devices
Symposium X: Advances in MEMS and Sensor Technologies
*Stella Kuei-Ann Wen , Professor and Vice Dean of R&D division, National Chiao Tung University,Hsinchu Taiwan, China
Integration of MEMS in existing IC lines: Toward Sensor and Microelectronics-system Integration for Life Enhancement
*Zai-fa Zhou,Professor, Deputy Director of Key Laboratory of MEMS of Ministry of Education,Southeast University
In situ test structures for material property of thin films in MEMS applications
*Jianfei Sun, Associate Professor, Southeast University, China
Magnetic field-controlled assembly of magnetic nanoparticles for potential biomedical application
** Xinxin Li, Prof. Director, State Key Lab of Transducer Technology,SIMIT- CAS, China
Cheaper or smarter: help MEMS chips leave the bloody road
* Yeon Sik Jung, Professor, Korea Advanced Institute of Science and Technology (KAIST), Korea
Fast and Convenient Sensing of Molecules by Printed 3D Superlattice Nanostructures
* Inkyu Park, Professor, Korea Advanced Institute of Science and Technology (KAIST), Korea
Flexible and stretchable transducers based on functional nano composites
*Huikai Xie, Professor, University Florida, USA
A Palm-size Near Infrared Fourier Transform MEMS Spectrometer
**Dr. Hendrik F. Hamann, IBM T. J. Watson Research Center
From Sensors to Smarter IoT Solutions
**Viorel DRAGOI, Chief Scientist, EV Group
Wafer-Level Bonding for High-Vacuum MEMS Manufacturing
*Shu-Min Kathy Li , Professor, National Sun Yat-Sen University
Layout-Aware Optimized Pre-bond Silicon Interposer Test Synthesis
*Tsung-Yi Ho, Professor, National Tsing Hua University
Digital Microfluidic Biochips: Towards Hardware/Software Co-Design and Cyberphysical System Integration
**Ulf Schlichtmann, Professor, Technical University of Munich
The Next Frontier in IC Design: Determining (and Optimizing) Robustness and Resilience of Integrated Circuits and Systems
*Haibao Chen, Assistant Professor, the Department of microelectronics, SJTU
Interconnect Reliability Modeling and Analysis for Multi-Branch Interconnect Trees
*Li Jiang, Assistant Professor, the Department of Computer Science & Engineering, Shanghai Jiaotong University
On Diagnosable and Tunable 3D Clock Network Design for Lifetime Reliability Enhancement
*Yuan Ji, Professor, Shanghai University
Stochastic logics for low cost and low power wearable applications
**Zhihua Wang, Professor of Electronic Engineering, Deputy Director of the Institute of Microelectronics, Tsinghua University, Chairman of IEEE Solid-State Circuit Society Beijing Chapter,an official member of China National
Wearable & Implantable Medical application – a challenge to integrated RF transceiver design
*Ngai Wong, Associate Professor of EEE Department, the University of Hong Kong
Constructive Tensor Outer-Product Decompositions With Applications in Circuit Modeling and Simulation
*Dong Xiang, Full Professor of School of Software, Tsinghua University
Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill
*Hailong Yao, Assistant Professor, Department of Computer Science and Technology, Tsinghua University
Flow-Control Co-Design Methods for Flow-Based Microfluidic Biochips
*Zuochang Ye, Associate Professor, Institute of Microelectronics, Tsinghua University
Application of Machine Learning in Circuit Optimization and Yield Analysis
*Shouyi Yin, Professor, Tsinghua University
High level synthesis for coarse-grained reconfigurable computing
*Zhi-Liang Qian, Assistant Professor, Shanghai Jiaotong University
Network-on-Chips (NoCs) based Multicore System: Performance Modeling, Architecture Optimization and Applications
**David Pan, Professor, U Texas at Austin
Nanolithography and Design Technology Co-optimization in Extreme Scaling
Symposium XII: Si Materials and Photovoltaic
*Dan Hu, Sr. Analyst, IHS Solar
Current Market for High Efficiency Solar Cells and Module
*Ted Guo, General Manager,ENN
Heterojunction Solar Cells and their Manufacturing
*Nam-Gyu Park, Professor, Sungkyunkwan University
High Efficiency Perovskite Cells
*Wenjin Wang, Director, IEE CAS
Device Physics of PERC Solar Cells
*Frank Liu, Professor, Shaanxi Normal University
Current Status of High Efficiency Perovskite Cells
*Jinyan Zhang, R&D Director, Hanergy
Rear Emitter Heterojunction Solar Cells
*Ivan Gordon, Manager, IMEC
Epi- emitter solar cells
*DengYuan Song, CTO, Yingli
High Efficiency n-type c-Si Solar Cells
*Jinjyuan Chen, VP, Ideal Energy
PECVD for Heterojunction Solar Cells
*LuLu Chen, VP, Archers
RPD for Heterojunction Solar Cells
*Guoqiang Xing, CTO, CSI
High Efficiency PERC Solar cells
*Tadashi Yoshihara, Sr. Manager, ULVAC
Cat-CVD and PVD for Heterojunction Solar Cells
*Chen Wang, R&D Director, GCL
The technology of multi-crystalline silicon wafers
*Peidong Liu, Senior expert of R&D center, LONGi silicon material co., LTD
The research and development of N type monocrystalline silicon wafer for high efficiency solar cells
