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English
March 20-22, 2019
Shanghai New International Expo Centre

Scott Sikorski

Scott Sikorski
Vice President of Group Technology Strategy & Product Technology Roadmap for JCET Group

Biography

Dr. Scott Sikorski joined STATS ChipPAC in 2009 after a 20 year career with IBM Microelectronics during which time he held positions related to semiconductor packaging in R&D, Manufacturing, Product Line Management, Business Management, and Marketing. Upon joining STATS ChipPAC, Dr. Sikorski was responsible for the Wirebond and Test product line areas. He is the Vice President of Group Technology Strategy and is now working on the product technology roadmap for JCET Group. Dr. Sikorski received his Bachelor of Science degree from Columbia University’s School of Engineering and Applied Sciences in Metallurgical Engineering and his Master’s degree and Ph.D. from the Massachusetts Institute of Technology, both in Materials Engineering.

Abstract

The semiconductor market enjoyed a year-over-year (YoY) increase in revenue of +20%, reaching a record high of $438.5M in 2017. Memory accounted for the majority of this increase, surging +58% YoY to $126.5B. In parallel with the exciting Memory commercial success is an equally exciting set of technical advancements in both the semiconductor as well as packaging areas. This presentation will discuss how packaging technology is evolving to meet the needs of tomorrow’s memory devices in both the volatile and non-volatile memory segments. Volatile memory is seeing two trends. First, advanced applications like graphics (GDDR5/6) have utilized advanced flip chip packaging, and this trend is expected to propagate steadily into DDR and LPDDR applications. Second, applications with very high bandwidth demands like advanced GPU and network server products are using High Bandwidth Memory (HBM) technology where a stack of four Through Silicon Via (TSV)-interconnected die are attached to the substrate via flip chip interconnect. Non-volatile memory has long relied on the stacking of die in a staircase configuration with each die individually wirebonded to the substrate. This trend continues with 16 die stacks or even 2 columns of 16 die stacks for the highest memory density applications like Solid State Disk Drives (SSD), placing incredible demands on the assemblers. In addition, high performance applications like mobile application processors (APs) have dramatic bandwidth and speed needs that require very close proximity between the logic and memory, driving integration at the packaging level. The Outsourced Semiconductor Assembly and Test (OSAT) industry, including the JCET Group, is responding with advances in process capabilities to help meet all of these needs while positioning to serve the aggressive domestic Chinese memory agenda.