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Dr. Jiang Yan North China University of Technology, China |
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Experience 2017 - present Dean /Professor/Expert of China Global Expert Recruitment program “Plan 1000” Electronics Engineering Department North China University of Technology 2009 – 2017 Institute of Microelectronics of Chinese Academy of Sciences (Beijing, China) Professor § Research for 14nm FDSOI § Study for 22nm bulk technology § Development for 32/28nm technology July’99 –July’09 Infineon Technologies (East Fishkill, NY, USA) Process Engineer / Project manager § Key process module development for 90nm, 65nm, 45nm, and 32nm nodes § FEOL process integration for low power application § Technology development for eDRAM and eFlash § eFuse design for 32nm technology Aug.’92–July’99 The University of Texas at Austin (Austin, TX) Research Assistant § Ultrathin gate dielectrics such as oxynitrides, SiO2, Si3N4, and BST. § CVD processes including RTCVD and MOCVD. § Characterization and analysis for CMOS devices. § Temperature measurement in RTP using acoustic method. Nov.’86–Aug.’92 Institute of Microelectronics of Chinese Academy of Sciences (Beijing, China) Process Engineer § Silicide processes for TiSi2, TaSi2, and WSi2. § LPCVD system set up and the process. § Ta2O5 dielectric Education 1995–1999 The University of Texas at Austin (Austin, TX) § Ph.D., Electrical Engineering. 1983–1986 Institute of Semiconductors of Chinese Academy of Sciences (Beijing, China) § M.S., Electrical Engineering. 1978–1983 University of Science and Technology of China (Hefei, China) § B.S., Semiconductors. US Patent 1. 7298009, Semiconductor method and device with mixed orientation substrate 2. 7186622, Formation of active area using semiconductor growth process without STI integration 3. 6,864,151, Method of forming shallow trench isolation using deep trench isolation 4. 7517767, Forming conductive stud for semiconductive devices 5. 7504309, Pre-silicide spacer removal 6. 7495279, Embedded flash memory devices on SOI substrates and methods of manufacture thereof 7. 7482215, Self-aligned dual segment liner and method of manufacturing the same 8. 7393746, Post-silicide spacer removal 9. 5,578,848, Ultra thin dielectric for electronic devices and method of making same 10. 5,478,765, Method of making an ultra thin dielectric for electronic devices. |
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