TSV and Other Key Enabling Technologies for 3D IC/Si   Integration and WLP
(Evolution, Challenge, and Outlook of 3D IC/Si Integration)

 

Date and Venue

09:00 - 17:00, March 20, 2012
Kerry Hotel Pudong, Shanghai, China (Shangri-la Group)

INSTRUCTOR:John H. Lau, ITRI Fellow

Abstract

3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration, which will be discussed in this lecture. Emphases are placed on the key enabling technologies for 3D IC/Si integrations, such as TSV (through-silicon via) forming and filling, front and back-side metallization, RDL (redistribution layer), IPD (integrated passive devices), temporary wafer bonding, wafer thinning and handling, wafer de-bonding, thin chip/wafer strength measurement and improving, W2W bumpless bonding, lost-cost lead-free microbumping (≤15µm pitch) and assembly, low-temperature wafer bumping and C2C, C2W, and W2W bonding, and thermal management. Useful characterization and reliability data for 3D IC integration will also be provided. The application of 3D IC integration such as CMOS image sensor, MEMS, LED, memory + logic, logic + logic, memory + microprocessor, active and passive interposers will be presented. More than 15 companies’ passive interposes (samples) used as substrates, carriers, and thermal management tools will be presented and discussed. Furthermore, the critical issues of TSV and 3D IC integration will be given and some potential solutions or research topics will be recommended. Finally, TSV manufacturing yield and hidden costs will be discussed and several roadmaps of 3D IC/Si integration will be provided. All the materials are based on the technical papers and books published within the past 3 years by the lecturer and others.

Who Should Attend?

If you (students, engineers, and managers) are involved with any aspect of the electronics, LED, MEMS, and optoelectronic industry, you should attend this course. It is equally suited for R&D professionals and scientists. You will receive more than 300 pages of handouts from the Instructor’s books, “Advanced MEMS Packaging” (McGraw-Hill, 2010) and “Reliability of RoHS Compliant 2D & 3D IC Interconnects” (McGraw-Hill, 2011)

Dr. John H. Lau ITRI Fellow, Industrial Technology Research Institute, Taiwan

Lecture Outlines

• Introduction
• Origin of 3D Integration
• Overview and outlook of 3D IC packaging
• Overview and outlook of 3D IC integration
• Overview and outlook of 3D Si integration
• TSV forming (DRIE and laser)
• TSV dielectric, barrier, and seed-metal layers
• TSV filling and CMP
• Fabrication and characterization of TSV interposers/chips
• Fabrication and characterization of 3D IC chip stacking
• Reliability of TSV interposers/chips
• Effects of TSV interposer on thermal performances
• Effects of TSV interposer on mechanical performances
• Glass interposers
• Interposers filled with W and CNT
• Stress sensor for thin-chip strength measurement
• Wafer thinning and thin-wafer handling
• Cu-Cu bumpless W2W bonding
• SiO2 -SiO2 bumpless W2W bonding
• Low-cost lead-free microbumps (≤15µm pitch): fabrication and characterization
• Low-cost lead-free microbumps (≤15µm pitch): assembly and reliability
• Low temperature (≤180oC) lead-free C2C, C2W, and W2W bonding
• 3D IC chip stacking with low temperature bonding
• CMOS image sensor with TSV
• 3D MEMS and IC integration
• 3D LED and IC integration
• Wide I/O memory, interface, and DRAM
• Equivalent thermal conductivities for copper-filled TSV interposer/chip
• Thermal management (design charts and guidelines) for 3D stacked chips
• Integrated liquid cooling solutions for 3D IC stacked modules
• Hot spots in thin chips for 3D IC stacking
• Embedded 3D hybrid IC Integration SiP With TSV for Opto-Electronic Interconnects
• Supply chain for 3D IC integration
• Critical issues in adopting TSV and 3D IC integration
• Some 3D IC/Si integration roadmaps
• Summary